Computer Architecture 10 Intel 8051 Microcontroller Made wi th OpenOffi ce.org 1 8051 Facts DevelopedDeveloped byby IntelIntel inin 1980,1980, CISC,CISC, HarvardHarvard architecture,architecture, singlesingle chipchip microcontroller,microcontroller, becomebecome thethe industryindustry standardstandard tilltill now!now! MostMost popularpopular inin thethe 1980s1980s andand earlyearly 1990s,1990s, todaytoday supersededsuperseded byby enhancedenhanced devicesdevices withwith 8051-8051- compatiblecompatible processorprocessor corescores ManufacturedManufactured byby moremore thanthan 2020 independentindependent manufacturers:manufacturers: Atmel,Atmel, InfineonInfineon Technologies,Technologies, MaximMaxim ,, NXPNXP ,, Winbond,Winbond, STST Microelectronics,Microelectronics, SiliconSilicon LaboratoriesLaboratories ,, TexasTexas InstrumentsInstruments andand CypressCypress SemiconductorSemiconductor Made wi th OpenOffi ce.org 2 Main Features 8-bit8-bit datadata busbus andand 8-bit8-bit ALUALU 16-bit16-bit addressaddress busbus -- 6464 kBkB ofof RAMRAM andand ROMROM On-chipOn-chip RAMRAM -- 128128 (256)(256) bytesbytes ("Data("Data Memory")Memory") On-chipOn-chip ROMROM -- 44 kBkB ("Program("Program Memory")Memory") FourFour 8-bit8-bit bi-directionalbi-directional input/outputinput/output portsports OneOne (two)(two) UARTUART (serial(serial port)port) TwoTwo 16-bit16-bit timerstimers Two-levelTwo-level interruptinterrupt prioritypriority PowerPower savingsaving modemode AllAll modernmodern versionsversions areare CMOSCMOS Made wi th OpenOffi ce.org 3 cont. TheThe originaloriginal 80518051 corecore ranran atat 1212 clockclock cyclescycles perper machinemachine cycle,cycle, withwith mostmost instructionsinstructions executingexecuting inin oneone oror twotwo machinemachine cyclescycles WithWith aa 1212 MHzMHz clockclock frequency,frequency, thethe 80518051 achievedachieved 1MIPS1MIPS (for(for one-cycleone-cycle instructions)instructions) EnhancedEnhanced 80518051 corescores runrun atat six,six, four,four, two,two, oror eveneven oneone clockclock perper machinemachine cycle,cycle, andand havehave clockclock frequenciesfrequencies ofof upup toto 100100 MHzMHz HigherHigher speedspeed singlesingle cyclecycle 80518051 corescores (<150MHz)(<150MHz) areare availableavailable forfor useuse inin FPGAsFPGAs andand (>150MHz)(>150MHz) inin ASICsASICs Made wi th OpenOffi ce.org 4 Distinct Features Bit-levelBit-level booleanboolean logiclogic operationsoperations cancan bebe carriedcarried outout directlydirectly andand efficientlyefficiently onon internalinternal registersregisters andand RAMRAM –– especiallyespecially valuedvalued inin industrialindustrial controlcontrol applicationsapplications FourFour separateseparate registerregister sets,sets, whichwhich cancan bebe usedused toto greatlygreatly reducereduce interruptinterrupt latencylatency -- fasterfaster thanthan storingstoring interruptinterrupt contextcontext onon aa stackstack Made wi th OpenOffi ce.org 5 Enhanced Versions ● built-in reset timers with brown-out detection ● on-chip oscillators ● self-programmable Flash ROM program memory ● bootloader code in ROM ● EEPROM non-volatile data storage ● I²C, SPI, and USB host interfaces ● PWM generators ● analog comparators ● A/D and D/A converters ● RTCs ● extra counters and timers ● in-circuit debugging facilities ● more interrupt sources ● extra power saving modes. Made wi th OpenOffi ce.org 6 Memory Map EA – controls low program-memory source PSEN, RD and WR signals are generated for external memories during instruction fetch (PSEN) or external data access with MOVX instructions (RD or WR) Made wi th OpenOffi ce.org 7 Internal Data Memory High-RAM (128B), register indirect addressing only, (not available in some microcontrollers) SFR – Special Function Registers, direct addressing only ● Low-RAM (128B) ● 4-banks of internal registers: RB0 – RB3 (00h-1Fh), 7-registers (R0-R7) in each bank ● Stack area – initial address 07h (grows towards higher addresses, SP on last element) ● Bit-addressable space (20h – 2Fh) ● General purpose space (30h – 7Fh) ● direct or indirect addressing modes possible Made wi th OpenOffi ce.org 8 Low Data RAM 128B 7Fh General purpose RAM 30h Bit-addressable memory Bit addresses from 00h to 7F (128bits = 16B) 20h RB3 RB2 RB1 R7 7h SP initial value R6 R5 R4 R3 RB0 R2 Current Register Bank (RB) selected by R1 bits in state (PWS) register R0 0h Made wi th OpenOffi ce.org 9 SFR ACC – Accumulator B – Aux. accumulator PWS – uC state register DPH, DPL – 16bit data pointer SP – Instruction & Stack pointers P0,P1,P2,P4 – I/O ports data registers IE – Interrupt mask IP,IPH – Interrupt priority registers PCON – Power-save control register TCON,TMOD – Timer control registers TL0,TH0 – 16-bit timer register AUXR – Aux. control bits Enhanced versions of microcontroller introduce other specific registers Made wi th OpenOffi ce.org 10 Architecture Overview Made wi th OpenOffi ce.org 11 Port 1 – Typical I/O I/OI/O withwith weakweak pull-uppull-up (50k-100k)(50k-100k) simplifiedsimplified directiondirection settingsetting (1(1→→D:D: InputInput Pin)Pin) Made wi th OpenOffi ce.org 12 Port 0&2 – Memory Interface MemoryMemory interfaceinterface independentindependent fromfrom I/OI/O settingssettings WeakWeak pull-uppull-up oror openopen draindrain Made wi th OpenOffi ce.org 13 Port 3 – Alternative Functions AlternativeAlternative inputinput andand outputoutput portport functionsfunctions Made wi th OpenOffi ce.org 14 Timer 0 (1) – Mode 0&1 TimerTimer countscounts upup andand rollsrolls overover allall 1s1s toto allall 0s0s ModeMode 0&1:0&1: 1313 oror 16-bit16-bit timertimer countercounter ClockedClocked byby uCuC oscillatoroscillator oror externallyexternally (Tx)(Tx) CountingCounting cancan bebe gatedgated internallyinternally oror externallyexternally (INTx)(INTx) Made wi th OpenOffi ce.org 15 Timer 0 (1) – Mode 2 8-bit8-bit timertimer countercounter TimerTimer countscounts upup andand andand isis reloadedreloaded fromfrom registerregister Made wi th OpenOffi ce.org 16 Timer 0 (1) – Mode 3 TwoTwo 8-bit8-bit independentindependent timerstimers TimerTimer 11 inin modemode 33 isis haltedhalted Made wi th OpenOffi ce.org 17 Timer 2 AvailableAvailable inin enhancedenhanced versionsversions 16-bit16-bit timer,timer, upup oror downdown countercounter 33 modesmodes ofof operation:operation: auto-reload, capture, baud rate generator Made wi th OpenOffi ce.org 18 Serial Interface ManyMany 8051s8051s areare equippedequipped withwith UARTUART operatingoperating inin threethree full-duplexfull-duplex modesmodes ModesModes ofof operationoperation areare highlyhighly configurable:configurable: frameframe format,format, parity,parity, baudbaud raterate AsynchronousAsynchronous transmissiontransmission andand receptionreception cancan occuroccur simultaneouslysimultaneously andand atat differentdifferent baudbaud ratesrates Made wi th OpenOffi ce.org 19 Baud Rate – Mode 1&3 TheThe baudbaud ratesrates inin ModesModes 11 andand 33 areare determineddetermined byby thethe TimerTimer 11 oror TimerTimer 22 overflowoverflow raterate TheThe BaudBaud RateRate GeneratorGenerator forfor transmittransmit andand receivereceive clocksclocks cancan bebe selectedselected separatelyseparately Made wi th OpenOffi ce.org 20 Commonly Used Baud Rates TimerTimer 11 vsvs oscillatoroscillator frequencyfrequency Made wi th OpenOffi ce.org 21 Interrupt System ExternalExternal InterruptsInterrupts TimerTimer InteruptsInterupts UARTUART InterruptsInterrupts InterruptInterrupt requestsrequests bits:bits: IE0, IE1, TF0, TF1, TF2, EXF2, RI, TI IndividualIndividual interruptinterrupt masks:masks: EX0, EX1, ET0, ET1, ET2, ES GlobalGlobal interruptinterrupt maskmask –– 1bit1bit EAEA Made wi th OpenOffi ce.org 22 Interrupt System IE0 EX0 IE1 EX1 TF0 ET0 TF1 ET1 RI TI ES TF2 EXF2 ET2 EA Made wi th OpenOffi ce.org 23 Interrupt Priorities InterruptInterrupt ofof higherhigher prioritypriority levellevel interruptsinterrupts thethe executionexecution ofof lowerlower prioritypriority levellevel interruptinterrupt TheThe finalfinal cyclecycle inin thethe executionexecution ofof thethe instructioninstruction cannotcannot bebe interruptedinterrupted RETIRETI oror anyany accessaccess toto thethe IEIE oror IPIP registersregisters cannotcannot bebe interruptedinterrupted Made wi th OpenOffi ce.org 24 Interrupt Vectors InterruptInterrupt vectorsvectors areare fixedfixed toto thethe beginningbeginning ofof instructioninstruction memorymemory IfIf interruptsinterrupts areare used,used, thethe firstfirst instructioninstruction mustmust bebe LCALLLCALL (3B)(3B) toto thethe mainmain programprogram Made wi th OpenOffi ce.org 25 Addressing Modes DirectDirect AddressingAddressing (e.g.(e.g. ADDADD A,7FHA,7FH)) operand is specified by an 8-bit address field in the instruction, only lowest 128B of internal Data RAM and SFRs can be directly addressed IndirectIndirect AddressingAddressing (e.g.(e.g. ADDADD A,@R0A,@R0)) instruction specifies a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed. The address register for 8-bit addresses can be R0 or R1 of the selected register bank, or the Stack Pointer. The address register for 16-bit addresses can only be the 16-bit “data pointer” register, DPTR. Made wi th OpenOffi ce.org 26 Addressing Modes ImmediateImmediate AddressingAddressing (e.g.(e.g. MOVMOV A,#100A,#100)) The value of a constant is included in the instruction opcode in Program Memory RegisterRegister DirectDirect (e.g.(e.g. ADDADD A,R7A,R7))