Generating Basic Software Platforms Reference Guide UG1138 (v2015.1) April 1, 2015 Revision History The following table shows the revision history for this document. Date Version Revision April 1, 2015 2.0 • Updated Pre-Synthesis Hardware Handoff Project Flow Images • Updated Post-Bitstream Tcl Projectless flow • Added name space to common Tcl commands. Existing scripts without namespaces in the commands work fine. However, using namespaces in all the commands is recommended to avoid any conflicts in future. • Updated Tcl Examples section with advanced configuration and multi block design • Added appendix C for generating software outputs from within Vivado • Added Appendix G for customized template applications (MAD) November 19, 2014 1.0 First version of the document Generating Basic Software Platforms www.xilinx.com Send Feedback 2 UG1138 (v2015.1) April 1, 2015 Table of Contents Revision History............................................................................................................... 2 Table of Contents ............................................................................................................ 3 Chapter 1: Introduction ........................................................................... 5 Chapter 2: Hardware Handoff.................................................................. 6 Pre-Synthesis Hardware Handoff ..................................................................................... 7 Post-Bitstream Hardware Handoff ................................................................................... 9 Chapter 3: Tcl Capabilities Overview ..................................................... 11 First Class Tcl Object Types and Relationships ............................................................... 12 Tcl Commands Listed by Category ................................................................................. 14 Chapter 4: Tcl Examples......................................................................... 17 Accessing Hardware Design Data................................................................................... 17 Creating Standalone Software Design and Accessing Software Information................... 20 Generating and Compiling Application with compiler settings and memory sections of choice.............................................................................................. 22 Generating and Compiling BSP with advanced driver/library/os/processor configuration ..................................................................................................... 22 Generating and Compiling BSP for a multi block design................................................ 24 Chapter 5: Input and Output Files......................................................... 26 Input Files ..................................................................................................................... 26 Output Files .................................................................................................................. 27 Generating Libraries and Drivers ................................................................................... 29 Appendix A: Obsolete Commands.......................................................... 33 Appendix B: Deprecated Commands...................................................... 35 Appendix C: BSP, DTS, and Application Generation in Vivado............... 41 Appendix D: Microprocessor Software Specification (MSS) ................... 43 MSS Overview............................................................................................................... 43 MSS Format................................................................................................................... 43 Global Parameters......................................................................................................... 44 Instance-Specific Parameters ......................................................................................... 45 Appendix E: Microprocessor Library Definition (MLD)........................... 50 Microprocessor Library Definition (MLD) Overview ....................................................... 50 MLD Library Definition Files .......................................................................................... 50 MLD Format Specification.............................................................................................. 51 MLD Parameter Descriptions ......................................................................................... 55 Appendix F: Microprocessor Driver Definition (MDD) ........................... 64 Microprocessor Driver Definition (MDD) Overview........................................................ 64 Generating Basic Software Platforms www.xilinx.com Send Feedback 3 UG1138 (v2015.1) April 1, 2015 MDD Driver Definition Files........................................................................................... 64 MDD Format Specification............................................................................................. 65 MDD Format Examples.................................................................................................. 65 MDD Parameter Description.......................................................................................... 67 MDD Keywords ............................................................................................................. 69 MDD Design Rule Check (DRC) Section.......................................................................... 73 MDD Driver Generation (Generate) Section................................................................... 74 Custom Driver ............................................................................................................... 74 Appendix G: Microprocessor Application Definition (MAD)................... 77 Microprocessor Application Definition (MAD) Overview................................................ 77 Microprocessor Application Definition Files................................................................... 77 MAD Format Specification............................................................................................. 78 MAD Format Example ................................................................................................... 79 Appendix H: HSI Tcl Commands ............................................................. 80 Tcl Commands Listed Alphabetically .............................................................................. 80 Appendix I: Additional Resources and Legal Notices ........................... 204 Xilinx Resources............................................................................................................204 Solution Centers ...........................................................................................................204 Please Read: Important Legal Notices ..........................................................................204 Generating Basic Software Platforms www.xilinx.com Send Feedback 4 UG1138 (v2015.1) April 1, 2015 Chapter 1 Introduction Hardware Software Interface (HSI) is a scalable framework enabling embedded SW tool integration with Vivado. It enables third-party OS vendors and software providers to distribute their software for Xilinx FPGA Platforms. HSI consumes hardware design (.hdf) files and the software repository (Drivers, OS, board support packages (BSPs), Libs, Apps, and DTG). It provides a rich set of Tcl APIs to access hardware information and to generate BSPs, Device Tree, and template applications. Figure 1–1: Design Flow Using HSI Generating Basic Software Platforms www.xilinx.com Send Feedback 5 UG1138 (v2015.1) April 1, 2015 Chapter 2 Hardware Handoff This chapter describes the Vivado hardware handoff flow for the pre-synthesis and post-bitstream designs. The figure below shows the IP integrator Zynq ZC702 example design. Figure 2–1: Example Zynq Design and Bus Functional Simulation Caution! Vivado hardware handoff flow supports only single Block Diagram and independent multi Block Diagram designs. It does not support RTL, Reference Block Diagram, and dependent multi-Block Diagram designs Generating Basic Software Platforms www.xilinx.com Send Feedback 6 UG1138 (v2015.1) April 1, 2015 Chapter 2: Hardware Handoff Pre-Synthesis Hardware Handoff GUI Project Flow Do the following to perform pre-synthesis hardware handoff in the Vivado interface. 1. Generate the block design. To do this: a. In the Flow Navigator, under IP Integrator, click Generate Block Design. The Generate Output Products dialog box opens. Generating Basic Software Platforms www.xilinx.com Send Feedback 7 UG1138 (v2015.1) April 1, 2015 Chapter 2: Hardware Handoff Figure 2–2: Generate Output Products Dialog Box b. Click Generate to generate the block design. 2. Export the hardware design. To do this: a. Select File > Export > Export Hardware. The Export Hardware dialog box opens. Figure 2–3: Export Hardware Dialog Box b. Leave the Include bitstream check box unchecked. c. Click OK to export the hardware design. Tcl Projectless Flow Use the following Tcl commands to perform pre-synthesis hardware handoff using Tcl commands outside of the Vivado project. 1. create_project –in_memory –part xc7z020clg484-1 2. set_property board_part xilinx.com:zc702:part0:1.0 [current_project] 3. read_bd base_zynq_design.bd 4. read_vhd base_zynq_design_wrapper.vhd 5. generate_target all [get_files base_zynq_design.bd] 6. write_hwdef -file base_zynq_design_wrapper.hdf Generating