PA RT THE HARDWA RE AND OPERATING SYSTEM 1: THE DEFINICON 68020 COPROCESSOR tem" on page 122 for complete dress decoding circuitry is shown in A plug--in board that information.) figure 3 and includes the FPU20 and The DSI-020 is a coprocessor board DEC20 PALs. the HOLD20 bus re­ provides 2--bit (see photo I) that uses the 12.5-mega­ quest arbiter PA L. the 32-bit bus DMA 3 hertz versions of the 68020 CPU and sequencer (74FI6I and DPORT20 computing power and the 6888I FPU (floating-point unit). PA L). the DSACK20 PAL. and the Provision has been made for the ad­ BE20 byte enable PA L (figure 4). The dition of the 688 51 PMMU (paged­ DSACK20 PA Ls main function is to math processing for memory-management unit) when it provide signals to the 68020 to in­ becomes available. The board has I dicate that a memory access cycle is 16--bit machines megabyte of high-speed parity­ complete and whether the size of the checked dynamic RAM that requires transfer was 8. I 6. or 3 2 bits. only one CPU wait state to operate A delay line and associated headers ave you ever wished that correctly. There are two high-speed delay the CPU's address strobe (AS) your personal computer (38.400 bps) serial ports (figure I) and signal long enough for all the de­ had the speed of a VA X an interrupt-driven timer to ease the coding to have been completed be­ or that the number 64K task of porting UNIX. fore the RASIN signal is generated to had never existed? We ll. the Motorola All the facilities of a host IBM PC or initiate the DP8409 dynamic RAM 68020 32-bit microprocessor has the compatible are available to the co­ controller's access cycle. The DP8409 computing power to come close to processor. including networking and (figure 5) directly drives the multi­ fulfillingH both those dreams. BYTE has access to any other peripherals con­ plexed address and RAS lines of the arranged for Definicon Systems to nected to the PC's bus. System calls RAMs. The CAS signal is multiplexed design a special version of its 68020- for full bit-mapped graphics are pro­ with the Byte Enable signals before based scientific microcomputer sys­ vided in the kernel. All BDOS and being applied to the RAM array, tem that allows 68020 hardware and BIOS software interrupts in the PC are shown in figure 6. The refresh counter software development at a price all available to the 68020 programmer. is driven from the CPU's clock oscil­ can afford. (See the text box "How to lator. divided by 128. The DP8409 at­ Get Yo ur DSI-020 Coprocessor Sys- OVERVIEW tempts to do a hidden refresh, but if The DSI-020 board is composed of a this is not possible, a refresh request Trevor Marshall. Christopher jones. and Sigi number of relatively independent (RFIO) will be sent to the HOLD20 Kluger are engineers with Definicon Systems functional blocks. The CPU cluster PA L every 10.24 microseconds. When Inc. They can be contacted at 3 I 324 Via Col­ (figure 2) consists of the 68020. this is acknowledged (with RFSHACK) inas #I08/9, Westlake Village, CA 9I 362. 6888 1. and 688 5 I. The 3 2-bit bus ad- the DP8409 will perform a RAS ONLY refresh cycle. Hidden refreshes occur whenever any device other than the RAM itself is addressed. In particular. accesses to the 68881 will cause a hidden refresh to occur. This considerably reduces any overhead that might otherwise be incurred using this DMA refresh technique. 120 BYTE • JULY J986 BY TREVOR MARSHALL, CHRISTOPHER }ONES, AND SIGI KLUGER Photo I: Tlie Definicon DSI-020 board with 68020 CPU. 68881 FPU. and I megabyte of memory. A 688 51 PMMU is shown with this board althougli it is not commercially available at this time. The parity error signal generated as implement virtual memory. The map­ and performs a memory cycle. The shown in figure 7 is latched and can ping from logical to physical ad­ special coding on the status lines in­ be read by the host PC at bit 0 of the dresses is stored in tables (in memory) dicates. ho·.vever. that the cycle is ac­ BFLAGS port (see table I and figure that the PMMU can search. It has an tually for the coprocessor interface. 4). Pulse the Refresh Inhibit line internal cache so that the most Chip select for the 68881 is derived 1 (RFSHINH) briefly to reset this latch. recently used translation table entries in the FPU20 PAL. are available without the necessity for The major feature of the 68881 is THE 68851 PMMU an additional bus cycle. The PMMU that many frequently used mathemat­ The principal function of the PMMU implements a hierarchical protection ical functions have been microcoded is the translation of logical addresses mechanism with up to eight access into the silicon. This considerably from the software running in the CPU levels. It also provides a breakpoint enhances the performance of the to physical addresses within the range acknowledge facility to support the 68020/68881 combination on engi­ of the available hardware facilities. 68020 breakpoint instructions. neering and scientific computations. This allows programs to run at ad­ The 688 51 internally decodes its It also accounts for its deceptively dresses that are not available in own chip select function. high performance on some function­ physical memory. An operating sys­ sensitive benchmarks. such as the tem that swaps infrequently used THE 6888 I COPROCESSOR Savage benchmark (Dr. Dobb's journal. memory blocks to disk and so en­ The 68881 is the first high-speed float­ March 1984. page 92). larges the effective addressing range ing-point accelerator from Motorola. of programs is called a virtual mem­ It is addressed when the 68020 places THE HOST PC BUS INTERFACE ory system (VMS). Although Definicon Ill on its status lines (FCO. FCI. and The IBM PC XT bus was designed as has written a VMS for the DSI-32. the FC2). 0010 on lines Al9 through Al6. a single master bus. so there is no kernel for the DSI-020 does not yet and 001 on lines Al5 through Al3 (continued) PHOTOG RAPHED BY PA UL AV IS JULY 1986 • BYTE 121 DEFINICON 68020 COPROCESSOR dynamic RAM refresh cycle. This (August 1985 BYTE. page 120) we The 8088 is used forces a coprocessor system such as found that the total replacement of the DSI-020 either to replace the 8088 the 8088 was relatively inefficient and to relieve the 68020 or to work in close cooperation with that it is capable of relieving the it. coprocessor of many of the tedious coprocessor of With the design of the PC AT. pro­ disk and console 1/0 tasks. The vision was made for a slave processor DSI-020 follows the same design to control the bus (via the ORO and criteria. The M5-DOS system on either many disk and console MASTER signals). but a limitation of a PC AT or a PC XT is used to pro­ 1 5 microseconds remains on the total vide file 1/0. networking. and other pe­ tasks. length of time a slave can keep con­ ripheral tasks. allowing the 68020 I/0 trol before memory refresh fails! This kernel to concentrate on the things it limit obviously makes it very difficult does best. The kernel provides the in­ method for a slave coprocessor to to provide safe direct disk or other terface and translation between the take control of the bus. tell the 8088 stream 110 tasks even using these UNIX-derived 68020 system software CPU to go to sleep. and drive the newer capabilities. It is for these and the facilities provided by M5-DOS peripherals directly. The XT relies on reasons that the DSI-020 is designed itself. We allowed the optional use of the 8088's DMA controller to take to transfer data 1 byte (or word) at a the 16-bit data transfer facility of the back control of the bus every . 15 time to the host environment. new AT bus. The majority of the im­ microseconds or so to perform a During the design of the OSI- 3 2 provement resulting from the use of How TO GET YO UR 051�020 COPROCESSOR SYSTEM Definicon Systems will provide . the a system with only floppy disks. a fixed Living Software BASIC to C Con- . elements of the DSI-020 system at the disk is essential for meaningful pro­ verter: $299 following special prices for BYTE gram development. Includes run-time package compiled readers. for compatibility with either SVS C Note: These special prices have been DSI-020 basic hardware: $99 5 or LLL C provided by Definicon. reducing its I megabyte of RAM. 12.5-MHz 68020. margins to a bare minimum. In par­ and !2.5-MHz 68881 SVS C: $349 ticular. no margin has been allowed for No parity chips or serial ports Kernighan and Ritchie definition with accounting overhead and so no purchase MS-DOS interface software. simplified most UNIX extensions orders can be accepted for these special assembler. linker. and assembly-level BYTE products. debugger Te rms of payment are VISA/Master­ The DSI-020 hardware is supplied fully LLL C: $349 Card/American Express only. There is assembled and tested. Kernighan and Ritchie definition with a 30-day. no-questions-asked. money­ most UNIX extensions back guarantee. Goods must be re­ Optional hardware upgrade: $99 turned in "as new" condition in original Chips for the two serial ports.