ComputerComputer HardwareHardware GenerationsGenerations • The First Generation, 1946-59: Vacuum Tubes, Relays, Mercury Delay Lines: – ENIAC (Electronic Numerical Integrator and Computer): First electronic computer, 18000 vacuum tubes, 1500 relays, 5000 additions/sec. – First stored program computer: EDSAC (Electronic Delay Storage Automatic Calculator). • The Second Generation, 1959-64: Discrete Transistors. • The Third Generation, 1964-75: Small and Medium-Scale Integrated (MSI) Circuits. • The Fourth Generation, 1975-Present: The Microcomputer. VLSI-based Microprocessors. EECC550 - Shaaban #1 Lec # 1 Winter 2001 12-4-2001 TheThe Von-Von-NeumannNeumann ComputerComputer ModelModel • Partitioning of the computing engine into components: – Central Processing Unit (CPU): Control Unit (instruction decode, sequencing of operations), Datapath (registers, arithmetic and logic unit, buses). – Memory: Instruction and operand storage. – Input/Output (I/O). – The stored program concept: Instructions from an instruction set are fetched from a common memory and executed one at a time. Control Input Memory - (instructions, data) Datapath registers Output ALU, buses Computer System CPU I/O Devices EECC550 - Shaaban #2 Lec # 1 Winter 2001 12-4-2001 CPU Machine Instruction Execution Steps Instruction Obtain instruction from program storage Fetch Instruction Determine required actions and instruction size Decode Operand Locate and obtain operand data Fetch Execute Compute result value or status Result Deposit results in storage for later use Store Next Determine successor or next instruction Instruction EECC550 - Shaaban #3 Lec # 1 Winter 2001 12-4-2001 HardwareHardware ComponentsComponents ofof AnyAny ComputerComputer Five classic components of all computers: 1. Control Unit; 2. Datapath; 3. Memory; 4. Input; 5. Output } Processor Computer Keyboard, Mouse, etc. Processor Memory Devices (active) (passive) Control Input (where Unit programs, data Disk Datapath live when Output running) Display, Printer, etc. EECC550 - Shaaban #4 Lec # 1 Winter 2001 12-4-2001 CPUCPU OrganizationOrganization • Datapath Design: – Capabilities & performance characteristics of principal Functional Units (FUs): – (e.g., Registers, ALU, Shifters, Logic Units, ...) – Ways in which these components are interconnected (buses connections, multiplexors, etc.). – How information flows between components. • Control Unit Design: – Logic and means by which such information flow is controlled. – Control and coordination of FUs operation to realize the targeted Instruction Set Architecture to be implemented (can either be implemented using a finite state machine or a microprogram). • Hardware description with a suitable language, possibly using Register Transfer Notation (RTN). EECC550 - Shaaban #5 Lec # 1 Winter 2001 12-4-2001 A Typical Microprocessor Layout: The Intel Pentium Classic EECC550 - Shaaban #6 Lec # 1 Winter 2001 12-4-2001 A Typical Microprocessor Layout: The Intel Pentium Classic EECC550 - Shaaban #7 Lec # 1 Winter 2001 12-4-2001 I/O I/O: Misc Memory CPU A Typical Personal I/O: Mass Storage Computer (PC) System Board Layout (90% of all computing systems worldwide). EECC550 - Shaaban #8 Lec # 1 Winter 2001 12-4-2001 ComputerComputer SystemSystem ComponentsComponents Proc Caches System Bus adapters I/O Buses Memory Controllers NICs Disks I/O Devices: Displays Networks Keyboards EECC550 - Shaaban #9 Lec # 1 Winter 2001 12-4-2001 Performance Increase of Workstation-Class Microprocessors 1987-1997 Integer SPEC92 Performance EECC550 - Shaaban #10 Lec # 1 Winter 2001 12-4-2001 MicroprocessorMicroprocessor LogicLogic DensityDensity 100000000 10000000 Alpha 21264: 15 million Moore’s Law Pentium Pentium Pro: 5.5 million PowerPC 620: 6.9 million i80486 1000000 Alpha 21164: 9.3 million i80386 Sparc Ultra: 5.2 million i80286 100000 i8086 Moore’s Law: 10000 i8080 2X transistors/Chip i4004 Every 1.5 years 1000 1970 1975 1980 1985 1990 1995 2000 Year EECC550 - Shaaban #11 Lec # 1 Winter 2001 12-4-2001 Increase of Capacity of VLSI Dynamic RAM Chips size year size(Megabit) 1000000000 1980 0.0625 100000000 1983 0.25 1986 1 10000000 1989 4 1000000 1992 16 100000 1996 64 1999 256 10000 2000 1024 1000 1970 1975 1980 1985 1990 1995 2000 1.55X/yr, Year or doubling every 1.6 years EECC550 - Shaaban #12 Lec # 1 Winter 2001 12-4-2001 ComputerComputer TechnologyTechnology Trends:Trends: RapidRapid ChangeChange • Processor: – 2X in speed every 1.5 years; 1000X performance in last decade. • Memory: – DRAM capacity: > 2x every 1.5 years; 1000X size in last decade. – Cost per bit: Improves about 25% per year. • Disk: – Capacity: > 2X in size every 1.5 years. – Cost per bit: Improves about 60% per year. – 200X size in last decade. • Expected State-of-the-art PC by end of year 2001 : – Processor clock speed: > 2500 MegaHertz (2.5 GigaHertz) – Memory capacity: > 1000 MegaByte (1 GigaBytes) – Disk capacity: > 100 GigaBytes (0.1 TeraBytes) EECC550 - Shaaban #13 Lec # 1 Winter 2001 12-4-2001 AA SimplifiedSimplified ViewView ofof TheThe Software/HardwareSoftware/Hardware HierarchicalHierarchical LayersLayers EECC550 - Shaaban #14 Lec # 1 Winter 2001 12-4-2001 HierarchyHierarchy ofof ComputerComputer ArchitectureArchitecture High-Level Language Programs Assembly Language Software Application Programs Operating Machine Language System Program Compiler Firmware Software/Hardware Instruction Set Architecture Boundary Instr. Set Proc. I/O system Datapath & Control Hardware Digital Design Microprogram Circuit Design Layout Register Transfer Logic Diagrams Notation (RTN) Circuit Diagrams EECC550 - Shaaban #15 Lec # 1 Winter 2001 12-4-2001 LevelsLevels ofof ProgramProgram RepresentationRepresentation temp = v[k]; High Level Language Program v[k] = v[k+1]; v[k+1] = temp; Compiler lw$15, 0($2) Assembly Language lw$16, 4($2) Program sw$16, 0($2) Assembler sw$15, 4($2) 0000 1001 1100 0110 1010 1111 0101 1000 Machine Language 1010 1111 0101 1000 0000 1001 1100 0110 Program 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Machine Interpretation Control Signal ALUOP[0:3] <= InstReg[9:11] & MASK Specification Register Transfer Notation (RTN) ° ° EECC550 - Shaaban #16 Lec # 1 Winter 2001 12-4-2001 AA HierarchyHierarchy ofof ComputerComputer DesignDesign Level Name Modules Primitives Descriptive Media 1 Electronics Gates, FF’s Transistors, Resistors, etc. Circuit Diagrams 2 Logic Registers, ALU’s ... Gates, FF’s …. Logic Diagrams 3 Organization Processors, Memories Registers, ALU’s … Register Transfer Notation (RTN) Low Level - Hardware 4 Microprogramming Assembly Language Microinstructions Microprogram Firmware 5 Assembly language OS Routines Assembly language Assembly Language programming Instructions Programs 6 Procedural Applications OS Routines High-level Language Programming Drivers .. High-level Languages Programs 7 Application Systems Procedural Constructs Problem-Oriented Programs High Level - Software EECC550 - Shaaban #17 Lec # 1 Winter 2001 12-4-2001 HardwareHardware DescriptionDescription • Hardware visualization: – Block diagrams (spatial visualization): Two-dimensional representations of functional units and their interconnections. – Timing charts (temporal visualization): Waveforms where events are displayed vs. time. • Register Transfer Notation (RTN): – A way to describe microoperations capable of being performed by the data flow (data registers, data buses, functional units) at the register transfer level of design (RT). – Also describes conditional information in the system which cause operations to come about. – A “shorthand” notation for microoperations. • Hardware Description Languages: – Examples: VHDL: VHSIC (Very High Speed Integrated Circuits) Hardware Description Language, Verilog. EECC550 - Shaaban #18 Lec # 1 Winter 2001 12-4-2001 RegisterRegister TransferTransfer NotationNotation (RTN)(RTN) • Dependent RTN: When RTN is used after the data flow is assumed to be frozen. No data transfer can take place over a path that does not exist. No statement implies a function the data flow hardware is incapable of performing. • Independent RTN: Describe actions on registers without regard to nonexistence of direct paths or intermediate registers. No predefined data flow. • The general format of an RTN statement: Conditional information: Action1; Action2 • The conditional statement is often an AND of literals (status and control signals) in the system (a p-term). The p-term is said to imply the action. • Possible actions include transfer of data to/from registers/memory data shifting, functional unit operations etc. EECC550 - Shaaban #19 Lec # 1 Winter 2001 12-4-2001 RTNRTN StatementStatement ExamplesExamples A ¬ B – A copy of the data in entity B (typically a register) is placed in Register A – If the destination register has fewer bits than the source, the destination accepts only the lowest-order bits. – If the destination has more bits than the source, the value of the source is sign extended to the left. CTL · T0: A = B – The contents of B are presented to the input of combinational circuit A – This action to the right of “:” takes place when control signal CTL is active and signal T0 is active. EECC550 - Shaaban #20 Lec # 1 Winter 2001 12-4-2001 RTNRTN StatementStatement ExamplesExamples MD ¬ M[MA] – Memory locations are indicated by square brackets. – Means the memory data register receives the contents of the main memory (M) as addressed from the Memory Address (MA) register. AC(0), AC(1), AC(2),AC(3) – Register fields are indicated by parenthesis. – The concatenation