EK-DXIIB-MM-002 DX11-8 system 360/370 channel to PDP-11 unibus interface maintenance manual digital equipment corporation • maynard, massachusetts 1st Edition, August 1972 2nd Printing (Rev) March 1973 3rd Printing July 1973 4th Printing May 1974 5th Printing (Rev) January 1976 Copyright © 1972,1973,1974,1976 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice. Digital Equipment Corporation assumes no respon­ sibility for any errors which may appear in this manual. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC PDP FLIP CHIP FOCAL DIGITAL COMPUTER LAB CONTENTS Page CHAPTER 1 GENERAL DESCRIPTION 1.1 Purpose of Manual 1-1 1.2 System Description 1-2 1.3 Mechanical Description 1-5 1.4 Specifications 1-5 1.4.1 Physical 1-6 1.4.2 Environmental 1-6 1.4:3 Electrical 1-6 1.4.4 Performance 1-6 1.5 Engineering Drawaing Drawings 1-7 CHAPTER 2 INSTALLATION AND ACCEPTANCE TEST 2.1 Summary of Installation Functions 2-1 2.2 Installation and Acceptance Test Requirements 2-2 2.2.1 Equipment Required 2-2 2.2.2 Diagnostics Required 2-2 2.2.3 Space Requirements 2-3 2.2.4 Power Requirements 2-3 2.2.5 Information Requirements 2-5 2.2.6 Test Schedule 2-6 2.3 Unpacking and Inspection 2-6 2.3.1 Unpacking 2-6 2.3.2 Inspection 2-7 2.4 Installation 2-7 2.4.1 PDP-II and DX11-B Cable Installation (within PDP-II System) 2-7 2.4.2 IBM Device Address Jumper Installation 2-8 2.4.3 Interrupt Vector Address Jumper Installation 2-12 2.5 Turning Power On for the First Time 2-12 2.6 PDP-II System Test Without DX11-B 2-13 2.6.1 Control and Indicator Panel Lamp Check 2-13 2.7 DX11-B Test Without IBM 360/370 (OffLine) 2-13 2.7.1 M306 NPR Timeout Mono Calibration Procedure 2-14 2.7.2 BLLM Calibration 2-15 2.7.3 Run the DX11-B Maintenance Clock 2 Test 2-15 (MAINDEC-11-DZDXF-[REV] -PB) 2.7.4 Run the DXII-B Off-Line Exerciser (MAINDEC-11-DZDXG-[REV] -PB) 2-15 2.8 DX11-B CABLE TEST 2-15 2.8.1 On Line B Delay Adjustment 2-18 2.8.2 DXTO Calibration Procedure 2-19 2.8.3 IBM 360/370 Cable Test Using DXII-B to Test Cables Without 2-19 IBM 360/370 System iii CONTENTS (Cont) Page 2.9 Filling Out Test Preparation Card 2-20 2.10 I/O Cable Requirements 2-21 2.11 Connecting DX11-B Cables To IBM Channel 2-21 2.12 EPO Cable Connection 2-24 2.13 EPO Panel Check 2-25 2.14 DX11-B System Test Using IBM 360/370 2-26 2.14.1 Introduction 2-26 2.14.2 Test Preparation 2-26 2.14.3 FRIEND Diagnostic Operating Procedure 2-27 2.14.4 Filling Out Test Preparation Card 2-31 2.14.5 Card Deck Preparation Procedure 2-31 2.14.6 DME/2848 Diagnostic Operation Procedures 2-34 2.14.7 Test Preparation 2-34 2.14.8 DME/2848 Diagnostic Operation Procedure 2-34 2.14.9 FRIEND or DME/2848 Diagnostic Operating Procedure for 3270 Console 2-38 2.15 Operating Suggestions 2-40 2.15.1 On-Line Operation Requirements 2-40 2.15.2 Errors with DME/2848 Diagnostic 2-41 2.15.3 Format Consideration and Logic Levels 2-41 2.16 Errors That Occur When FRIEND is Run 2-41 2.17 Maintenance Procedures 2-42 2.18 Hints on Interface Signal Monitoring While Troubleshooting 2-42 CHAPTER 3 OPERA nON 3.1 Scope 3-1 3.2 Controls and Indicators 3-1 3.3 861 Controls and Indicators 3-9 3.3.1 Pilot Lamps 3-9 3.3.2 Circuit Breaker 3-9 3.3.3 LOCAL/OFF/REMOTE Switch 3-9 3.3.4 Remote Switching Control Bus Connectors 3-9 CHAPTER 4 PROGRAMMING 4.1 Scope 4-1 4.2 IBM 360/370 and PDP-II Format Comparison 4-1 4.3 IBM 360/370/DX11-B Communication 4-2 4.4 DX11-B/PDP-ll Communication 4-2 4.5 DX11-B Formats 4-3 4.5.1 Device Status Register (DXDS) 4-4 4.5.2 Command and Address Register (DXCA) 4-6 4.5.3 Control Unit Status Register (DXCS) 4-7 4.5.4 Offset and Status Register (DXOS) 4-9 4.5.5 Bus Address Register (DXBA) 4-10 4.5.6 Byte Count Register (DXBC) 4-11 4.5.7 Maintenance Out Register (DXMO) 4-11 iv CONTENTS (Cont) Page 4.5.8 Maintenance In Register (DXMI) 4-13 4.5.9 Control Bits Register (DXCB) 4-14 4.5.10 Non-Processor Request Data Register (DXND) 4-16 4.5.11 Extra Signals Registers (DXESI and DXES2) 4-17 4.5.12 Maintenance Out Buffered Register (DXMOB) 4-18 4.6 Programming Considerations 4-18 4.6.1 Hardware/Software Interlock 4-18 4.6.2 Boundary Considerations 4-19 4.6.3 Interrupt Request 4-19 4.6.4 Data Transfer 4-20 4.6.5 Status Presentation 4-20 4.6.6 On-Line/Off-Line Control 4-20 CHAPTERS THEORY OF OPERATION 5.1 Scope 5-1 5.2 Functional Description 5-1 5.3 Block Diagram Discussion 5-2 5.3.1 IBM Interface Operation 5-3 5.3.2 IBM Control Operation 5-11 5.3.3 Unibus Interface Operation 5-12 5.3.4 PDP-II Control Operation 5-12 5.3.5 Central Control Operation 5-13 5.3.6 Channel Simulator Operation 5-14 5.4 Sequences of Operation 5-14 5.4.1 IBM Sequences 5-15 5.4.1.1 Selector Channel-Initiated Sequences (CHI) 5-15 5.4.1.2 Control Unit Initiated Sequences (CUI) 5-19 5.4.1.3 Reset Sequences 5-20 5.4.1.4 Multiplexer Channel Differences 5-22 5.4.1.5 IBM Sequence Summary 5-24 5.4.2 DXll-B Sequences 5-27 5.4.2.1 Register Organization 5-27 5.4.2.2 Flow Diagram Conventions 5-29 5.4.2.3 Design Flows 5-30 5.5 Circuit Descriptions 5-40 5.5.1 DXll Device Status Register (DXDS) 540 5.5.2 Control Unit Status Register (DXCS) 5-41 5.5.3 DXll Bus Address Register (DXBA) 541 5.5.4 DXll Byte Counter (DXBC) 542 5.5.5 Control Unit Status Register (CUSR) Part of DXOS 542 5.5.6 NPR Data Register (DXND) 5-43 5.5.7 DXll Control Bits Register (DXCB) 543 5.5.8 Control Lines Out Register (CONO) Part of DXMO 544 v CONTENTS (Cont) Page 5.5.9 Control Lines In Register (CONI) Part of DXMI 5-44 5.5.10 IBM Bus-In Lines (BUS!) Part of DXMI 5-45 5.5.11 Tumble Table Index (TTNDX) 5-45 5.5.l2 Control Unit Address Register (CUAR) Part of DXCA 5-45 5.5.13 Control Unit Command Register (CUCR) Part of DXCA 5-45 5.5.14 Unibus Interface 5-46 5.5.15 NPR and TNT Control 5-46 5.5.16 Data Bus Multiplexer 5-47 5.5.17 Clock, Phase and Time State Generator 5-47 5.5.18 Maintenance Out Buffered Register (DXMOB) 5-47 5.5.19 General Controls 5-48 5.5.20 Signals and Gates 5-48 5.5 .21 Parity and Address Compare 5-49 5.5.22 IBM Interface 5-50 5.5.23 Select Bypass and Power Fail 5-50 5.5.24 "Bit Slice" and "Select" Loop Trace in Off-Line Cable Mode 5-51 5.5.25 EPO Panel Operation 5-51 CHAPTER 6 MAINTENANCE 6.1 Introduction 6-1 6.2 Preventive Maintenance 6-1 6.2.l Mechanical Checks 6-1 6.2.2 Test Equipment Required 6-1 6.3 Corrective Maintenance 6-2 6.3.1 General Corrective Procedures 6-2 6.3.2 Diagnostic Testing 6-2 6.3.3 Vibration Tests 6-3 CHAPTER 7 ENGINEERING DRAWINGS 7.1 General 7-1 APPENDIX A REFERENCE MATERIAL A.l Glossary A-I A.2 HEX/OCTAL/EBCDIC Conversion Chart A-12 A.3 Hexadecimal/Octal Conversion A-13 APPENDIX B ADDRESS ASSIGNMENTS B-1 APPENDIX C INTRODUCTION TO DXI1-B FLOW DIAGRAMS C-l vi ILLUSTRATIONS Figure No. Title Page 1-1 DXll-B, System 360/370 Channel to PDP-II Unibus Interface 1-3 1-2 Typical DXll-B System Block Diagram 1-4 1-3 DXll-B Functional Block Diagram 1-5 2-1 H960 and H957 Cabinet Dimensions 2-4 2-2 DXll-B Cable Connections Configured for User Operation 2-8 (Viewed from Rear) 2-3 DXll - IBM Cable Assembly Configured to Execute Cable Loop 2-9 Around Test DZDXH 2-4 M908 Module Before Wiring 2-10 2-5 I/O Address Format 2-10 2-6 Example of Wiring for Four Devices 2-11 2-7 Example of Wiring for 16 Devices 10 through IF (1x) 2-11 2-8 Example of Wiring for 32 Devices 50 through 6F (5x and 6x) 2-11 2-9 Example of Wiring for One Device (10) 2-11 2-10 Example of Wiring for Two Devices (10 to 11) 2-12 2-11 Example of Wiring for 8 Devices (20-27) 2-12 2-12 NPR Timeout Mono Calibration Waveform 2-14 2-13 BLLM Calibration Signal 2-15 2-14 Test Bus Cable Connections Without IBM 360/370 Cables Supplied 2-16 By Customer 2-15 Test Bus Cable Connections Using IBM 360/370 Cables 2-17 2-16 S.ignal Flow for Test Cable Connections 2-18 2-17 Normal Cable Connections to Channel Bus if on End of Bus 2-22 2-18 Normal Cable Connections to Channel Bus if Not on End of Bus 2-23 2-19 Sample FRIEND 360/370 Console Printout 2-29 2-20 IBM 360/370 Console 2-30 2-21 Sample Prep Card 2-32 2-22 Test Preparation Card 2-33 2-23 Typical Line Printer Copy from the DME/2848 Diagnostic 2-35 2-24 Input/Output Signals 2-43 2-25 Formats for Transmission of Information on the Buses 2-43 3-1 DXll-B Controls and Indicators 3-2 3-2 Type 861-A,-B,-C Power Controller Panels ~-1O 4-1 IBM 360/370/PDP-ll Data Format Comparison 4-1 4-2 360/PDP-ll Transfer Conventions 4-3 4-3 Device Status Register Bit Assignments 4-4 4-4 Command and Address Register Bit Assignments 4-7 4-5 Control Unit Status Register Bit Assignments 4-7 4-6 Offset and Status Register Bit Assignments 4-10 4-7 Bus Address Register Bit Assignments 4-11 4-8 Byte Count Register Bit Assignments 4-11 4-9 Maintenance Out Register Bit Assignments 4-12 4-10 Maintenance In Register Bit Assignments 4-13 4-11 Control Bits Register Bit Assignments 4-14 vii ILLUSTRATIONS (Cont) Figure No.