Arm® System Memory Management Unit Architecture Specification SMMU architecture version 3 Document number ARM IHI 0070 Document version D.a Document confidentiality Non-confidential Copyright © 2016-2020 Arm Limited or its affiliates. All rights reserved. Arm System Memory Management Unit Architecture Specifica- tion Release information Date Version Changes 2020/Aug/31 D.a• Update with SMMUv3.3 architecture • Amendments and clarifications 2019/Jul/18 C.a• Amendments and clarifications 2018/Mar/16 C• Update with SMMUv3.2 architecture • Further amendments and clarifications 2017/Jun/15 B• Amendments and clarifications 2016/Oct/15 A• First release ii Non-Confidential Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of Arm. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, Arm makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, patents, copyrights, trade secrets, or other rights. This document may include technical inaccuracies or typographical errors. TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to Arm’s customers is not intended to create or refer to any partnership relationship with any other company. Arm may make changes to this document at any time and without notice. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail. The Arm corporate logo and words marked with ® or ™ are registered trademarks or trademarks of Arm Limited (or its affiliates) in the US and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow Arm’s trademark usage guidelines at http://www.arm.com/company/policies/ trademarks. Copyright © 2016-2020 Arm Limited (or its affiliates). All rights reserved. Arm Limited. Company 02557590 registered in England. 110 Fulbourn Road, Cambridge, England CB1 9NJ. LES-PRE-20349 version 21.0 ARM IHI 0070 Copyright © 2016-2020 Arm Limited or its affiliates. All rights reserved. iii D.a Non-confidential Contents Arm® System Memory Management Unit Architecture Specifi- cation Arm System Memory Management Unit Architecture Specification ............ ii Release information .................................. ii Non-Confidential Proprietary Notice .......................... iii Chapter 1 About this document 1.1 References ..................................... 12 1.2 Terms and abbreviations .............................. 13 1.3 Document Scope .................................. 17 Chapter 2 Introduction 2.1 History ........................................ 20 2.2 SMMUv3.0 features ................................ 21 2.3 SMMUv3.1 features ................................ 23 2.4 SMMUv3.2 features ................................ 24 2.5 SMMUv3.3 features ................................ 25 2.6 Permitted implementation of subsets of SMMUv3.x and SMMUv3.(x+1) archi- tectural features ................................... 26 2.7 System placement ................................. 27 Chapter 3 Operation 3.1 Software interface ................................. 30 3.2 Stream numbering ................................. 32 3.3 Data structures and translation procedure .................... 34 3.3.1 Stream Table lookup ............................ 34 3.3.2 StreamIDs to Context Descriptors ..................... 36 3.3.3 Configuration and Translation lookup ................... 40 3.3.4 Transaction attributes: incoming, two-stage translation and overrides .. 42 3.3.5 Translation table descriptors ........................ 43 3.4 Address sizes .................................... 44 3.4.1 Input address size and Virtual Address size ................ 46 3.4.2 Address alignment checks ......................... 47 3.4.3 Address sizes of SMMU-originated accesses ............... 47 3.5 Command and Event queues ........................... 50 3.5.1 SMMU circular queues ........................... 50 3.5.2 Queue entry visibility semantics ...................... 53 3.5.3 Event queue behavior ............................ 53 3.5.4 Definition of event record write “Commit” ................. 54 3.5.5 Event merging ................................ 54 3.5.6 Enhanced Command queue interfaces .................. 55 3.6 Structure and queue ownership .......................... 58 3.7 Programming registers ............................... 59 3.8 Virtualization .................................... 60 3.9 Support for PCI Express, PASIDs, PRI and ATS ................. 61 3.9.1 ATS Interface ................................ 61 3.9.2 Changing ATS configuration ........................ 68 3.9.3 SMMU interactions with CXL ........................ 69 3.10 Support for two Security states .......................... 70 ARM IHI 0070 Copyright © 2016-2020 Arm Limited or its affiliates. All rights reserved. iv D.a Non-confidential Contents 3.10.1 Secure State Determination (SSD) .................... 70 3.10.2 Secure commands, events and configuration ............... 71 3.10.3 Secure EL2 and support for Secure stage 2 translation ......... 73 3.11 Reset, Enable and initialization .......................... 75 3.12 Fault models, recording and reporting ....................... 78 3.12.1 Terminate model .............................. 80 3.12.2 Stall model .................................. 81 3.12.3 Considerations for client devices using the Stall fault model ....... 84 3.12.4 Virtual Memory paging with SMMU .................... 84 3.12.5 Combinations of fault configuration with two stages ........... 85 3.13 Translation table entries and Access/Dirty flags ................. 87 3.13.1 Software update of flags .......................... 87 3.13.2 Access flag hardware update ........................ 88 3.13.3 Dirty flag hardware update ......................... 88 3.13.4 HTTU behavior summary .......................... 89 3.13.5 HTTU with two stages of translation .................... 90 3.13.6 ATS, PRI and translation table flag update ................ 91 3.13.7 Hardware flag update for Cache Maintenance Operations and Destruc- tive Reads .................................. 92 3.14 Speculative accesses ............................... 93 3.15 Coherency considerations and memory access types .............. 94 3.15.1 Client devices ................................ 94 3.16 Embedded implementations ............................ 96 3.16.1 Changes to structure and queue storage behavior when fixed/preset .. 96 3.17 TLB tagging, VMIDs, ASIDs and participation in broadcast TLB maintenance . 98 3.17.1 The Global flag in the Translation Table Descriptor ............ 100 3.17.2 Broadcast TLB maintenance from Armv8-A PEs with EL3 in AArch64 . 101 3.17.3 Broadcast TLB maintenance from ARMv7-A PEs or Armv8-A PEs with EL3 using AArch32 ............................. 102 3.17.4 Broadcast TLB maintenance in mixed AArch32 and AArch64 systems and with mixed ASID or VMID sizes .................... 102 3.17.5 EL2 ASIDs and TLB maintenance in EL2 Host (E2H) mode ....... 103 3.17.6 VMID Wildcards ............................... 104 3.18 Interrupts and notifications ............................. 106 3.18.1 MSI synchronization ............................ 107 3.18.2 Interrupt sources .............................. 107 3.19 Power control .................................... 109 3.19.1 Dormant state ................................ 109 3.20 TLB and configuration cache conflict ....................... 110 3.20.1 TLB conflict ................................. 110 3.20.2 Configuration cache conflicts ........................ 110 3.21 Structure access rules and update procedures .................. 112 3.21.1 Translation tables and TLB invalidation completion behavior ....... 112 3.21.2 Queues ................................... 115 3.21.3 Configuration structures and configuration invalidation completion