Writing Testbenches: Functional Verification of HDL Models Second Edition Writing Testbenches: Functional Verification of HDL Models Second Edition by Janick Bergeron Qualis Design Corporation Springer Science+Business Media, LLC Libnry o( Congrtss Cataloging-in-Publiutio n Bergeron, Janick. Wriling testbenchcs: functional vcrification of HDL models! by Janick Bcrgeron.--2nd ed. p.em. ISBN 978-1-4613-5012-5 ISBN 978-1-4615-0302-6 (eBook) DOI 10.1007/978-1-4615-0302-6 I.Computer hardware description languages. 2.IntegJated ci rcuils--Vcrification. I. Tide. TK7885. 7. 8472003 621.38 I 5---dc21 2003041995 Copyright 0 200) by Springer Science+Business Media New York Originally published by Kluwc:r Academic Publishers in 2003 Softcovc:r reprint ofthe hardcover 2nd edition2oo3 All rights reserved. No pan of Ihis publication may bc reprodueed, stored in a retrieval system ortfansmilled in any fonn Of by any means, electronic, mechanical, photo-copying, mierofilming, recording, orotherwise, without the prior written pc:nnission ofthe publisher, with the exceptioll ofany material supplied specifically fOT the purposeofbeing entered and executed on a computer sySlem, for exclusive use by the purchaSoer ofthe work. Pennissions for books published in the USA: permissions@wkap . com Pennissions for books published in Eutopc: [email protected] Prinfed on acid-free paper. TABLE OF CONTENTS About the Cover xv .. Foreword XVll Preface XlX Why This Book Is Important ...•..•••....•..... xix What This Book Is About • • . • • . • . • . • • .. xx What Prior Knowledge You Should Have ..•.•..•• xxi Reading Paths • . • • • . • . • • . • . • .. xxii Choosing a Language •...................... xxiii VHDL vs. Verilog ........................... xxiii Hardware Verification Languages .............. xxiv And the Winner Is... .......................... xxv For More Information •........••..••...•...• xxvi Acknowledgements .....•••.....•.......••.. xxvi CHAPTER 1 What is Verification? 1 What is a Testbench? . • • . • • • • • . • . • . .. 1 The Importance of Verification . • . • •• 2 Reconvergence Model • • . • . • • • • • • . • • . .. 5 Writing Testbenches: Functional Verification of HDL Models v Table of Contents The Human Factor • • . • • . • • • • • . • • • . • . • •• 6 Automation . • • • • . • . 7 Poka-Yoke .............•...................... 7 Redundancy .....................••............ 7 What Is Being Verified? .•••••••••.•...•.•••••• 8 Formal Verification ............................. 8 Equivalence Checking .•..................•..•.• 9 Model Checking ............••..•.••.......... 10 Functional Verification ....•..............•.•..• 11 Functional Verification Approaches • • • • . • . • • • •• 12 Black-Box Verification ....•.................... 12 White-Box Verification ..••..................... 13 Grey-Box Verification ..................••....• 15 Testing Versus Verification . • . • • • • • • • • . .• 16 Scan-Based Testing .....................•....• 17 Designfor Verification ..•...............•.....• 18 Design and Verification Reuse . • • • . • . • • . • • • . •• 19 Reuse Is About Trust ..•..•..................... 19 Verification for Reuse ...............•.•.......• 20 Verification Reuse ...•.•....................... 20 The Cost of Verification • • • • . • • • • • • • • • • • • • • .. 21 Summary ....••••••••••..•.•••.•••.•...•.•• 23 CHAPTER 2 Verification Tools 25 Linting Tools . • . • . • . • . • • • • • • • . .. 26 The Limitations of Linting Tools ..••............•. 27 Linting Verilog Source Code .......••............ 29 Linting VHDL Source Code ...•..........••..... 30 Linting Open Vera and e Source Code ......•....... 32 Code Reviews .........•...................... 32 Simulators . • . • • . • • • • • . • • . • . • . •• 33 Stimulus and Response ......................... 34 Event-Driven Simulation ....................... 34 Cycle-Based Simulation ...•.................... 37 Co-Simulators .......••.......•.......•....... 39 Verification Intellectual Property •••....•••••..•• 42 Hardware Modelers ....•....•................. 43 Waveform Viewers . • • • • • • • • . • • • • • . • . • • •• 44 vi Writing Testbenches: Functional Verification of HDL Models Code Coverage . • . • . • . • • . • . • • . .• 46 Statement Coverage ........•........•......... 48 Path Coverage ..•...•........................ 51 Expression Coverage ......••.................• 52 FSM Coverage ...........•..................• 52 What Does 100% Code Coverage Mean? •......... 53 Functional Coverage • • • • • • • . • . • • • . • . • • • . .. 55 Item Coverage ...........................••..• 57 Cross Coverage .......•...............•....... 59 Transition Coverage ..........•................ 60 What Does 100% Functional Coverage Mean? •..... 61 Verification Languages • • • • • . • • . • • •. 62 Assertions . • • . • • . • . • • . • . • . • • . •• 64 Simulation Assertions .......................... 66 Formal Assertion Proving .................•.... 67 Revision Control • . • . • • . • • . • . • • • • . • . .• 68 The Software Engineering Experience .........•... 69 Configuration Management ........••........... 71 Working with Releases ......................... 72 Issue Tracking . • • . • • . • • • . • • • • • • . • . .. 74 What Is an Issue? ...•........•...............• 74 The Grapevine System ...........•............. 75 The Post-It System .........................••. 76 The Procedural System .....•............•...... 76 Computerized System ..................•..••... 77 Metrics • • . • • . • • • • • • • • • . • • • . • • • • . • • • . •• 78 Code-Related Metrics .......................... 79 Quality-Related Metrics ....••.................. 80 Interpreting Metrics .....................•..... 81 Summary •••••••••••••••••••••••••••••••••• 83 CHAPTER 3 The Verification Plan 85 The Role of the Verification Plan . • • • . • •• 86 Specifying the Verification ...................••. 86 Defining First-Time Success ......•.............. 87 Levels of Verification • • . • . • • • • • • • . • • • • •. 88 Unit-Level Verification ......................... 90 Reusable Components Verification ..............•. 91 ASIC and FPGA Verification .................... 92 Writing Testbenches: Functional Verification of HDL Models vii Table of Contents System-Level Verification ....................... 92 Board-Level Verification ..•.....••••.........•.. 93 Verification Strategies .........•...•..•.•. 94 Verifying the Response ......................... 95 From Specification to Features . • . • . • • • . .. 96 Component-Level Features ...................... 99 System-Level Features ......................... 99 Error Types to Look For ....................... 100 Prioritize ................................... 101 Designfor Verification ........................ 102 Directed Testbenches Approach . • . • • • • • • • •. 104 Group into Testcases .......................... 105 From Testcases to Testbenches .................. 106 Verifying Testbenches ......................... 107 Measuring Progress ...................•...... 108 Coverage-Driven Random-Based Approach ...••. 109 Measuring Progress .......................... 109 From Features to Functional Coverage ........... 111 From Features to Testbench .................... 113 From Features to Generators .......•........... 115 Directed Testcases ............................ 118 Summary • . • . • • • . • • . • . • • . • . .. 120 CHAPTER 4 High-Level Modeling 121 Behavioral versus RTL Thinking . • . .. 121 Contrasting the Approaches .................... 123 You Gotta Have Style! ....................... 125 A Question of Discipline ....................... 125 Optimize the Right Thing ....................•• 126 Good Comments Improve Maintainability ......... 129 Structure of Behavioral Code • • • • • . • • . • •. 130 Encapsulation Hides Implementation Details ...... 131 Encapsulating Useful Subprograms .............. 134 Encapsulating Bus-Functional Models ............ 137 Data Abstraction ..........••..•..•......•.• 145 Records ...................•................ 146 Variant Records .............................. 151 Arrays ..................................... 155 Lists .....................................•. 157 viii Writing Testbenches: Functional Verification of HDL Models Files ...................................... 163 Mapping High-Level Data Types to Physical Interfaces 165 Object-Oriented Programming •••••••••••••••• 166 Classes ...........................•........ 166 Inheritance ................................. 173 Polymorphism ............................... 177 Limitations of Open Vera and e S OOP Implementation. 180 Aspect-Oriented Programming .••••.•••••.•..• 181 The Problem with Object-Oriented Programming ... 181 Variant Data with Variant Code ... " ......•..... 183 Limitations of e's AOP Implementation ........... 186 The Parallel Simulation Engine •••• • • • • • . • • • • •. 189 Connectivity, Time and Concurrency ..........•.. 189 Connectivity, Time and Concurrency in HDLs and HVLs ..................................... 190 The Problems with Concurrency ................. 191 Emulating Parallelism on a Sequential Processor ... 192 The Simulation Cycle ......................... 194 The Co-Simulation Cycle ........ " ............ 196 Parallel vs. Sequential ........................ 197 Fork/Join Statement .......................... 199 The Difference Between Driving and Assigning ..... 205 Race Conditions • • • • • • • • • • • • • . • • • • • • • • •• 208 ReadlWrite Race Conditions .................... 209 WritelWrite Race Conditions ..................