State University of New York at Stony Brook ESE 314 Electronics Laboratory B Department of Electrical and Computer Engineering Fall 2012 © Leon Shterengas ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ Lab 1: MOSFET current sources. 1. OBJECTIVES Study and characterize MOSFET-based current sources: IV characteristics of MOSFETs; Operation of current mirrors; Basic and Wilson current mirrors. 2. INTRODUCTION 2.1. MOSFET modeling and operation. Proper modeling of the MOSFET current-voltage (IV) characteristics becomes increasingly complicated in modern IC technology where separation between source and drain became smaller that 50 nm and gate oxide thicknesses are order of nm. Clearly, for our laboratory experiments we are not going to delve into this extremely complicated subject. We are going to rely on VERY simplified equations that are coming from large MOSFET era. Strictly speaking, even for large MOSFETs they are only approximations but it would serve our purpose. After this necessary excuse we write down the equation for MOSFET IV: W α 2 VGS VT VSB I DS COX μ VGS VT VSB VDS VDS , VDS , (1) L 2 α W V V V 2 V V V I C μ GS T SB , V GS T SB , (2) DS L OX 2 α DS α where IDS drain-to-source current, W – channel width, L – channel length, COX – gate oxide capacitance per unit area, µ - charge carrier mobility in channel, VGS – gate-to-source voltage, VT(VSB) – threshold voltage that, generally, depends on source-to-bulk voltage (VSB) due to body effect, VDS – drain-to-source voltage, α – coefficient with value between 1 and 2 that takes care about change of the transistor threshold along channel due to body effect. It is often assumed that α is equal to 1 and we adopt this convenient simplification (however, you should be aware that it usually leads to overestimation of the drain-to-source current in saturation). Equation (1) models MOSFET IV in so called triode or nonsaturation mode, i.e. before channel pinch-off or carrier velocity saturation. We will be mostly concerned about MOSFET operation in saturation mode (Equation (2)). One more thing has to be mentioned – finite output resistance of the MOSFET in saturation, i.e. dependence of the drain-to-source current on drain-to-source voltage in saturation. This is often unwanted effect but it has to be taken into account. Hence, for saturation we have: W V V V 2 I κ GS T SB 1 λ V , V V V V V , (3) DS L n 2 DS DS GS T SB DSsat where λ – is so called channel length modulation parameter (kn – transconductance process parameter, i.e. product of µ and COX). It was indeed mostly channel length modulation effect that accounted for the finite output resistance of the MOSFETs when they were large. These days proximity effects of the source and drain govern the finite output resistance physics. However, again for the sake of simplicity we will use this old 1 State University of New York at Stony Brook ESE 314 Electronics Laboratory B Department of Electrical and Computer Engineering Fall 2012 © Leon Shterengas ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ parameterization in our modeling. It is common practice to use parameter VA (like Early voltage in BJT) to characterize MOSFET output resistance. Early voltage is equal to inverse of channel length modulation parameter, i.e. VA = 1/λ. The equation (3) constitutes the basis for SPICE LEVEL 1 MOSFET model (LEVEL 3 model includes α, and there are a lot more specific models). Proper form of expression to model body effect, i.e. dependence of VT on VSB depends on technology of the particular MOSFET. Classical form of the expression is: VT VSB VT 0 γ Δ VSB Δ , where VT(0) – threshold voltage with zero voltage between source and bulk, Δφ – is voltage drop across semiconductor in strong inversion for zero source-to-bulk voltage, and γ – body effect coefficient. In CMOS IC body effect plays very important role since it is impossible to maintain VSB = 0. However, whenever possible we will eliminate this effect from our labs though you should always remember that it needs to be taken care of when dealing with real world IC (wait for your ESE 311). Equation (3) can be used to estimate MOSFET output resistance and gate transconductance. 1 1 I W V V V 2 V Output resistance: r DS λ κ GS T SB A , (4) O n VDS L 2 I DS VGS I W W DS Gate transconductance: g m κ n VGS VT VSB 2 κ n I DS , (5) VGS L L VDS These two small signal parameters relate small variations of the drain-to-source and gate-to-source voltages to corresponding variations of drain-to-source current. Circuit in Figure 1 below can be used to characterize the transistor gate transconductance. In this circuit the gate of the MOSFET is connected to its drain (diode-connected MOSFET), thus the VDS = VGS > VGS – VT = VDSsat, i.e. transistor is always in saturation provided that VDD1 is above VT. By adjusting the value of the resistance of the potentiometer RREF one can vary the drain current ID1. By setting RREF to some convenient value and by changing VDD1 one can obtain dependence of ID1 on gate-to-source voltage VGS1. R REF VDD1 ID1 M1 VGS1 0 Figure 1. 2 State University of New York at Stony Brook ESE 314 Electronics Laboratory B Department of Electrical and Computer Engineering Fall 2012 © Leon Shterengas ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ 2.2. Basic current mirror. Consider the circuit in Figure2a where the gate of M2 is connected to the gate of M1. Assume that both transistors are identical and have infinite output resistances (λ = 0). Since gate-to-source voltages of both MOSFETs are the same, than ID2 should be equal to ID1 as long as VDD2 is bigger than VDSsat. Hence, ID1 is “mirrored” to ID2. The circuit is called current mirror. Generally, ID2 can be different from ID1 because of difference in parameters between transistors M2 and M1. The output current can be scaled by adjusting the W/L ratios. MOSFET current mirrors are also useful in providing a simple way of generating multiple currents for different stages of a circuit. An example of a two-output MOSFET current source is shown in Figure 2a. R REF VDD2 VDD3 R REF R L2 R L2 R L3 VDD2 ID1 ID1 VDD1 ID2 VDD1 ID2 ID3 M1 M2 VDS2 M1 M2 M3 VGS1 VGS1 0 (a) 0 (b) Figure 2. Ideally ID2 should be constant regardless of the load that was connected between power supply and drain of M2 (RL2 in Figure 2). In that respect, M2 would act as a current source for its load. Realistically, ID2 is dependent upon the drain-to-source voltage of M2 (VDS2), due to finite output resistance of M2. 2.3. Wilson current mirror. Load for M2 in Figure 2a could be another MOSFET based circuit that uses ID2 as a bias current. Bias current determines the values of small signal parameters and the stabilization of the bias current is important task, see equations (4) and (5). Ideally this bias current should be provided by current source with infinite output impedance. For the circuit in Figure 2a that would mean that ID2 should be independent of VDS2. Clearly it is not the case and ID2 changes with VDS2. In other words, the real current source made of basic current mirror has output impedance equal to small signal output resistance of M2. Circuit in Figure 2a can be used to measure the output resistance of M2 by measuring ID2 as a function of VDD2. The output impedance of the bias current source can be improved by using more elaborate designs of the current mirrors. Students are encouraged to read the corresponding section on improved current mirrors in recommended book. One possible way of improvement is to use Wilson current source. Wilson current source (Figure 3) provides better overall performance than the simple current mirror. The output impedance of the Wilson current source is increased from output resistance of MOSFET M2 (rO2) to rO2 multiplied by open circuit gain of M3 (gm3 multiplied by rO3). Note, however, that there is a disadvantage to stacking devices as in the Wilson current source: every device must be kept in saturation in order to operate properly for analog purposes, and that implies that at least VDSsat 3 State University of New York at Stony Brook ESE 314 Electronics Laboratory B Department of Electrical and Computer Engineering Fall 2012 © Leon Shterengas ¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯ must be maintained across every device. With a fixed amount of voltage available from the power supply, using more of it in a stacked current source leaves less for the load itself. R L3 I REF ID3 M3 VDD1 VDD3 M2 M1 VGS1 0 Figure 3. We will use individual enhancement mode NMOS transistors for this introductory lab. The pin-out and approximate values of the basic parameters of the 2N7000 MOSFETS are given in Figure 4. If in doubt about FET pin-out compare the currents flowing between leftmost and rightmost terminals under ±1V bias. Drain- source diode get forward biased when source is positive and drain is negative. VT 2.1 V 2 (W/L)*µn*C’OX 180 mA/V V 50 V A Figure 4. Pin-out and generic transconductance IV for 2N7000 NMOS. In our lab we use transistors in package marked 2N7000 on front side (top side in picture above). 3. PRELIMINARY LAB 3.1. For the circuit in Figure 1 assume VDD1 = 6 V and RREF = 100 Ω.