Embedded Peripheral IP User Guide Subscribe UG-01085 101 Innovation Drive 2014.24.07 San Jose, CA 95134 Send Feedback www.altera.com TOC-2 Contents Introduction........................................................................................................ 1-1 Tool Support.................................................................................................................................................1-1 Obsolescence.................................................................................................................................................1-1 Device Support............................................................................................................................................. 1-2 Document Revision History.......................................................................................................................1-2 SDRAM Controller Core.....................................................................................2-1 Core Overview..............................................................................................................................................2-1 Functional Description............................................................................................................................... 2-1 Avalon-MM Interface......................................................................................................................2-2 Off-Chip SDRAM Interface............................................................................................................2-2 Board Layout and Pinout Considerations.................................................................................... 2-3 Performance Considerations..........................................................................................................2-4 Configuration............................................................................................................................................... 2-4 Memory Profile Page....................................................................................................................... 2-5 Timing Page......................................................................................................................................2-6 Hardware Simulation Considerations.......................................................................................................2-7 SDRAM Controller Simulation Model......................................................................................... 2-7 SDRAM Memory Model.................................................................................................................2-7 Example Configurations............................................................................................................................. 2-8 Software Programming Model...................................................................................................................2-9 Clock, PLL and Timing Considerations................................................................................................... 2-9 Factors Affecting SDRAM Timing................................................................................................ 2-9 Symptoms of an Untuned PLL.....................................................................................................2-10 Estimating the Valid Signal Window..........................................................................................2-10 Example Calculation......................................................................................................................2-11 Document Revision History.....................................................................................................................2-13 Tri-State SDRAM................................................................................................ 3-1 Feature Description..................................................................................................................................... 3-1 Block Diagram..................................................................................................................................3-2 Configuration Parameter............................................................................................................................3-2 Memory Profile Page....................................................................................................................... 3-2 Timing Page......................................................................................................................................3-2 Interface.........................................................................................................................................................3-3 Reset and Clock Requirements.................................................................................................................. 3-8 Architecture.................................................................................................................................................. 3-8 Avalon-MM Slave Interface and CSR........................................................................................... 3-9 Block Level Usage Model................................................................................................................ 3-9 Document Revision History.....................................................................................................................3-10 Altera Corporation TOC-3 Compact Flash Core............................................................................................ 4-1 Core Overview..............................................................................................................................................4-1 Functional Description............................................................................................................................... 4-1 Required Connections.................................................................................................................................4-2 Software Programming Model...................................................................................................................4-3 HAL System Library Support.........................................................................................................4-3 Software Files....................................................................................................................................4-3 Register Maps................................................................................................................................... 4-4 Document Revision History.......................................................................................................................4-5 Common Flash Interface Controller Core..........................................................5-1 ........................................................................................................................................................................ 5-1 Core Overview..............................................................................................................................................5-1 Functional Description............................................................................................................................... 5-2 Configuration............................................................................................................................................... 5-2 Attributes Page................................................................................................................................. 5-2 Timing page...................................................................................................................................... 5-3 Software Programming Model...................................................................................................................5-3 HAL System Library Support.........................................................................................................5-4 Software Files....................................................................................................................................5-4 Document Revision History.......................................................................................................................5-4 EPCS Serial Flash Controller Core..................................................................... 6-1 Core Overview..............................................................................................................................................6-1 Functional Description............................................................................................................................... 6-2 Avalon-MM Slave Interface and Registers................................................................................... 6-3 Configuration..............................................................................................................................................6-4 Software Programming Model...................................................................................................................6-4 HAL System Library Support.........................................................................................................6-4 Software Files....................................................................................................................................6-5