Virtual Address Translation Dealing With Large Page Tables Using TLBs to Speedup Address Translation Multi-level paging Cache recently accessed page-to-frame translations in a TLB Add additional levels of For TLB hit, physical page number obtained in 1 cycle indirection to the page table For TLB miss, translation is updated in TLB by sub-dividing page number into k parts Has better than 99% hit ratio !! (why?) Second-Level f o Create a “tree” of page Page Tables Physical tables CCPPUU Addresses 16 10 9 1 p o Virtual Address Virtual p2 Addresses 20 10 9 1 ? p1 p2 p3 o Key Value p3 p f f p1 Third-Level TLB p First-Level Page Tables X Page Table Page Table 11 12 Dealing With Large Page Tables Virtual Address Translation Multi-level paging Using Page Registers (aka Inverted Page Tables) Example: Two-level paging Each frame is associated with a register containing Residence bit: whether or not the frame is occupied CCPPUU MMeemmoorryy Occupier: page number of the page occupying frame Protection bits p p o f o 1 2 Virtual Physical Addresses Addresses 20 16 10 1 16 10 1 Page registers: an example Physical memory size: 16 MB Page size: 4096 bytes Number of frames: 4096 f PPTTBBRR ++ page table ++ Space used for page registers (assuming 8 bytes/register): 32 Kbytes p1 p2 Percentage overhead introduced by page registers: 0.2% First-Level Second-Level Size of virtual memory: irrelevant Page Table Page Table 13 14 Page Registers Inverted Page Tables Tradeoffs Searching for a Virtual Page Advantages: If the number of frames is small, the page registers can be Size of translation table occupies a very small fraction of placed in an associative memory physical memory Size of translation table is independent of VM size Virtual page number looked up in associative memory Hit: frame number is extracted Disadvantages: Miss: results in page fault We have reverse of the information that we need…. How do we perform translation ? Limitations: Search the translation table for the desired page number Large associative memories are expensive Memory expansion is non-trivial 15 16 Dealing With Large Inverted Page Tables Searching Inverted Page Tables Using Hash Tables Using Hash Tables Use a proven fast search technique: Hash Tables Hash page numbers to find corresponding frame numbers in a “frame” table with one entry per page frame Page registers are placed in an array CCPPUU MMeemmoorryy Page i is placed in frame f(i) where f is an agreed-upon PID p o f o Virtual Physical “hashing function” rrunniunningng Addresses 20 9 1 Addresses 16 9 1 To lookup page i, perform the following: Hash Hash TTaablblee Compute f(i) and use it as an index into the table of page registers f – 1 max Extract the corresponding page register PPTTBBRR + PID 0 1 0 page fmax– 2 Check if the register contains i, if so, we have a hit h(PID, p) Otherwise, we have a miss 0 Inverted Page Table 17 18 Searching the Inverted Page Table Virtual Memory (Paging) Using Hash Tables (Cont’d.) The bigger picture Codeode Daattaa A process’s VAS is its context Minor complication Contains its code, data, and stack Since the number of pages is usually larger than the number of SSttaacckk slots in a hash table, two or more items may hash to the same location Code pages are stored in a user’s file on disk Some are currently residing in memory; most are not Two different entries that map to same location are said to collide Data and stack pages are also stored in a file Although this file is typically not visible to users File System File only exists while a program is executing Many standard techniques for dealing with collisions (Disk) Use a linked list of items that hash to a particular table entry OS determines which portions of a process’s Rehash index until the key is found or an empty table entry is VAS are mapped in memory at any one time OS/MMU reached … Physical Memory 19 20 Virtual Memory Virtual Memory Performance Page fault handling Physical Page fault handling analysis Memory To understand the overhead of paging, compute the References to non-mapped pages effective memory access time (EAT) generate a page fault EAT = memory access time × probability of a page hit + CCPPUU page fault service time × probability of a page fault Page fault handling steps: 0 Service the fault Page Example: Block the running process Table Memory access time: 20 ns Read in the unmapped page Disk access time: 25 ms Resume/initiate some other process Let p = the probability of a page fault Map the missing page into memory Program EAT = 20(1–p) + 25,000,000p Restart the faulting process P’s VAS To realize an EAT within 5% of minimum, what is the largest value of p we can tolerate? Disk 21 22 Virtual Memory Summary Physical and virtual memory partitioned into equal size units Size of VAS unrelated to size of physical memory Virtual pages are mapped to physical frames Simple placement strategy There is no external fragmentation Key to good performance is minimizing page faults 23.