SiD Status and Plans International Workshop on Linear Colliders Morioka, 5 Dec 2016" Overview" R&D and software developments" Collaboration activities" Outlook" Aidan Robson for the SiD Consortium P SiD A compact, cost-constrained detector designed to make precision measurements and be sensitive to a wide range of new phenomena 5T coil! rinner=2.6m" return yoke & muon chambers" vertex detector" HCAL! 5 layers barrel+disk" 40 layers" rinner=1.4cm" silicon strip tracker! 5 layers" ECAL! 30 layers" router=1.25m" Aidan Robson 2/23 SiD tracking A robust, low-material, high-precision silicon system Vertex Detector Challenging requirements:! Technology choice comes later:! <3µm hit resolution! Si diode pixels (‘standard’ tech)" Feature size ~20µm" Monolithic designs! ~0.1% X0 per layer ! (MAPS, Chronopix)" material budget! Vertically integrated (‘3d’) " <130µW/mm2! approaches (VIP chip)! Single-bunch timing ! High-Voltage CMOS resolution Silicon strip tracker Silicon microstrips, 25µm pitch / 50µm readout! 5 barrel layers / 4 disks! Tracking unified with vertex detector – 10 layers in barrel! Gas-cooled" Material budget <20% X0 in active region! Readout using KPiX ASIC bump-bonded to module Aidan Robson 3/23 MAPS development Baseline readout for SiD tracker and ECal is KPiX CMOS monolithic approach! kPixM-Trk! kPixM-Cal! Integrate sensors and front-end Pixel size! 40x500 µm2" 1000x1000 µm2" Array! 200x2400" 100x94" electronics on the same substrate" Stitched 5x5 Stitched 5x5 Full Size! reticles" reticles" Potential for: Max. Signal! 1fC" 1pC" Effective ENC! <200e- " <1000e- " Lower material budget! Filtering! LP + CDS" LP + CDS" S/N! >20" >4" Smaller pixel size! In pix mem. depth! 1 bucket" 16 buckets" Lower costs" ADC resolution! 12 bits" 12 bits" DC Power cons.! ~ 20µW/pix " ~ 20µW/pix " kPixM Test structure submission: Power pulsing ! Yes " Yes" Technology LFoundry 150nm on high resistivity substrate (2k#cm) thinned to 150µm (fully depleted with 80V)" Passive pixels (40µm x 500µm)! Active pixels (8 variants of 40µm x 500µm)! Mosfet arrays for technology characterization" => Being produced now SLAC, Oregon Aidan Robson 4/23 Chronopix Baseline readout for SiD vertex detector Series of three Chronopixel prototypes:! Timestamping" (300ns period)! "Sparse readout! "demonstrated with v1" "Pulsed power " "NMOS electronics with acceptable power consumption " Comparator" offset calibration works! v2" ! Many problems solved; concept proven valid! Derived capacitances:" Opt 1 – 9.04 fF, ! ! Sensor diode capacitance an issue for 90nm process" Opt 2 – 6.2 fF, ! Prototype 3 had six sensor options to study Opt 3 – 2.73 fF, ! Signal from Fe55 " sensor diode capacitance – large sensor Opt 4 & 5 4.9 fF,! 5.9 keV X-rays" capacitance in 90nm technology appears solved! Opt 6 – 8.9 fF " PoS (Vertex2015) 038" Need to fully understand sensor operation details, measure sensor efficiency for MIPs! Cross-talk issues have been addressed by separating analogue and digital power and adding small decoupling capacitor. Some minor cross-talk persists – will try to minimise more! Prototype 3 chips at Yale! => MIPs and rad-hardness measurements in progress" Oregon, Yale Aidan Robson 5/23 Tracker sensors ! tracker sensor prototypes from Hamamatsu from 2008 became damaged by wirebonding (oxide layer between Metal 1 and 2 inadequate)" ! not pursued for several years" ! renewed interest in 2016 (both SiD and ILD) and favourable negotiations with Hamamatsu; oxide layer thickness will be increased and Under Bump Metallization will be provided! """ " " " => going ahead! Working towards full prototype test: ! sensor + KPiX + cables" SLAC, Oregon, Davis, UNM, DESY Aidan Robson 6/23 Tracker support structures New effort! upper layer modules sit here ! Aim to build structures (including services and cooling) ! with lengths of several metres and less than 1% X0" hoop ! Supports consist of CFRP box channels! joint "– ultra-high modulus skins! "– high moment of inertia! "– manageable dimensions" ! Services are co-cured into the structure! lower layer modules sit here ! Also investigating possibilities for linking ! cooling the box channels" channels Modules on top and bottom for two strip system 20-30cm" adjacent layers " First prototype" Tongue-and-groove for possible linking to next channel" FEA studies done" U of Oxford, U of Lancaster, U of Liverpool Aidan Robson 7/23 Pair background envelope Re-analysed pair background envelope in beam pipe New analysis! ! with current beam pipe design, around 0.45% of all particles leave tracks outside the beam pipe! ! could consider reducing beam pipe radius by 2mm! ! could consider an additional vertex detector layer for SiD" GuineaPig" beam pipe" old study! r (mm) 20 (different! machine" parameters)" 10 0 0 100 200 300 400 500 " DESY !!! ! z [mm]! z [mm]! Aidan Robson 8/23 ECal Highly granular ‘imaging’ calorimetry essential for ILC physics programme: ! Particle ID/reconstruction" ! Tracking charged particles " ! Integral part of Particle ! Flow detector design" ! Baseline design: silicon / tungsten Aidan Robson 9/23 ECal sensors Major lessons so far…: ! Bump bonding to sensors with Al pads can be very difficult! "– sensor foundry build final pad stack – Under Bump Metallization" ! Sensors with ROCs can have issues with parasitic couplings! "– shield pixel traces! In present design, metal 2 traces from pixels to pad array run over other pixels: parasitic capacitances cause crosstalk." New scheme has “same” metal 2 traces, but a fixed potential metal 1 trace shields the signal traces from the pixels." SLAC, Oregon, UC Davis Aidan Robson 10/23 ECal sensors All shield traces are tied together, New prototypes with KPiX attached" and brought to a metal 2 pad." Shield trace running under metal 2 signal trace. " connection of implant to metal 2 trace to pad." Testing underway, preparing SLAC, Oregon, UC Davis for cable attachment" Aidan Robson 11/23 SiW ECal testbeam analysis –9 Testbeam profile x10 GeV (mm) y ! 9-layer Si/W calorimeter! ! ~6X0! 2 ! 13mm pixels" ! 12.1GeV electrons" New analysis! x (mm) Two electron ! Two electron ! separation separation distribution efficiency normalised to 100 events 0 10 20 30 40 50 separation (mm) Oregon, SLAC, UC Davis separation (mm) -> See talk by A. Steinhebel in Cal session (Wed pm)" Aidan Robson 12/23 HCal Following a review, new baseline technology for the SiD HCal is Scintillator / SiPM / Steel Work ongoing to compare simulated single-particle energy resolution with CALICE testbeam results To come: mechanical design work following rebaselining UTA Aidan Robson 13/23 Solenoid 5T field 30º design Recent redesign of barrel / door junction: Baseline CMS conductor ! More efficient ! ! Easier transport /! 200" flux return handling <50 Gauss at 15m field(Gauss) Bz 0 0 distance from beamline ( m ) 25 SLAC Aidan Robson 14/23 Muon idenQfier / calorimeter tail catcher SiD baseline: long scintillator strips with WLS fibre and SiPM readout Yoke/Muon system changes since DBD:" 8x 12x ! Consistent extension of the baseline HCal scintillator technology" ! Need to optimize number of layers, strip dimensions" Aidan Robson 15/23 Forward region layout Recent studies have looked at different aspects of the forward region layout Set of related questions: ! Is the anti-DID necessary?! ! What is the optimum forward calorimeter (BeamCal) shape?! ! What buffer depth is required for forward/ inner detectors?" DID: Detector-integrated Dipole" More aggressive approach" to removing material from the path of backgrounds! Trade-off between BeamCal reconstruction efficiency and albedo effect UCSC, SLAC Aidan Robson 16/23 Vertex detector occupancy Forward region design can affect vertex detector occupancy: x10–6 From IP/inner detector using BeamCal 500 GeV backscatter lumi upgrade New analysis! Detector occupancies:! Phi (radians)" with/without anti-DID! Background pairs hits different beam holes" can arrive microseconds -> robust after the beam crossing -> able to reject with DESY see arXiv:1609.07816" timing cuts Aidan Robson 17/23 Forward calorimeter buffer size " Radius(mm) Buffer Depth" Occupancy" Detailed study of dominant low-angle backgrounds" using latest beam parameters" Many channels in forward ECal have ~10 hits per train! Depth of 4 buffers -> lose around 10–3 of hits! Depth of 6 buffers -> lose around 10–4! see arXiv:1609.07816" –4 -> need 8 buffers to maintain losses below 10 for innermost radii UCSC Aidan Robson 18/23 Beam-related muon background Shield detectors from muons from beam delivery sys Magnetized spoilers intended to sweep muons from BDS into tunnel walls" Is magnetized wall also necessary?" Simulated with MUCARLO from BDS plus full Geant 4 SiD detector simulation" spoilers only ECcalEndcap occupancy very high without wall" New analysis! Occupancy, SiTrackerEndcap" Occupancy, ECalEndcap" 1" 1" 5 spoilers! 5 spoilers" + wall" 5 spoilers! –6" 10–6" + wall" 10 5 spoilers" spoilers plus wall 0 5 10 15 20 25" 0 10 20 30 40 50 60 70" N hits per cell" N hits per cell" SLAC, DESY -> see talk by A. Schuetz in MDI session (Thurs)" Aidan Robson 19/23 Simulaon & reconstrucQon At LCWS15, SiD decided to implement DD4HEP simulation and common reco Implemented geometry and drivers! Updated to latest digitizers! Developing performance benchmarking tools! Currently commissioning full conformal pattern ! recognition (as implemented by CLICdp) & Pandora PFA" Relies on close hit residuals ! collaboration/support (vertex detector)" from CLICdp and ILD developers" track parameter pulls" resolutions" New! -> See