Digital Technical Tournal Digital Equipment Corporation Managing Editor Richard W Beam Edltor Jane C. Dlak Pcoductloa St& Production Editor - Helen 1 Partenon Designer - Charlotte Bell Typographers -Jonathan M. Bohy Macgaret Burdine lllusultor - Deborah Kc~lcy Advisoiy Board Samuel H. Fuller, Chairman Robert M. Glorioso John W. McCredle Mahendra R. Patel F. Grant Saviers William D. Srrcckr Victor A. Vyssutsky The Digital Technical Journal is published by Digital Equipment Corporatloa, 77 Reed Road, Hudson, Magsachu~etts0 1749. Changes of address should be sent to Digital Equipment Corporation. attention: List Maintenance. I0 Forbes Road, Northboro, MA 01532 Please indude the address label wlth changes marked. Comments on the content of any paper arc welcomed. Write to the editor at Mall Stop HL02.3/K11 at the published~bpaddress. Comments can ahbe sent on the BNET to RDVAX: :BIAKEor on the ARPANET to B~%RDVAX.DE~DE~. Copyright @ 1988 Digital Equipment Corporation. Copying without fee is permitted provided that such copies are made for use in educational lnstltutions by faculty members and are nor distributed for commercial advantage. Abstncting with credit of Digital Equipment Corporation's authorship is permltted. Requests for other copies for a Pee may br made to Digiul Press of Digital Equipment Corporation. A11 rights reserved. The information in this journal is subject to change without notice and should not bc construed as a com- mltment by Digital Equipment Corporation. Digital Equipment Corpmtion assumes no responslbllity for any errors that may appcss in this document ISSN 0898.901X Documentatlcm Number EY-6742H-DP The following are wademarks of Digital Gquipmcnt Corporation: ALL.IN-I. DEQNA, HSC70. I. 1 1. MicmVAX, MicroVAX 11, MicroVAX 3000, NMI, NOTES, Qbbus, Q22-bus, Rh81, R.482, RD54, RQDX3, RX50, TKSO, ULTRIX-32, VAX, VAX-11/780, VAX-11/782, VAX 6200, -.- -.- VAX 6210, VAX 6220, VAX 6230, VM 6240, VAX 8200, @##tWt# @3 Dl'fMf 'J dBrUrCBd Gil#fXS @@&&DmOne VAX 8300, VhX 8650, VAX 8800, VAX 8840, VAXBI, JiW!4mdtnmtanre, m~o~wfa~i~sflrrVAXELN, VAX MACRO, VAX SPM, VAX/vMS, VMS. krsMC# &WH%W4? S&~O?B a WE Of Compu-Share is a trademark of Compu-She. Jnc. W tehaaJogy. 72w 81:@- qfLW f~pqgmmsrb GDS I1 is a uademvk of Calma Corpora~iua. pq&mmtmpaw#& the gptm wEm&W$y Mtbr new SPICE is a trademark of the University of Calliornia at m-q-. berkcley Tektronix and DAS are trademarks of Tehniu. Lor Book produalon was done by Digital's Eduatiml Services Mtdia Communications Group in Bedford. Mh Contents 8 Foreword Robert M. Supnik CVAX-based Systems 10 An Overview of the VAX 6200 Family of Systems Brian R. Allison 19 The Architectural Definition Process of the VAX 6200 Family Brian R. Allison 2 8 Interfacing a VAX Microprocessor to a High-speed Multiprocessing Bus Richard B. Gillett, Jr. 47 The Rok of Computer-aided Engineering in the Design of the VAX 6200 System Jean H. Basmaji, Glenn P. Gamey, Masood Heydari, and Arthur L. Singer 5 7 VMS Symmetric Multiprocessing Rodney N. Gamache and Kathleen D. Morse 64 Perfomance Evaluation of the VAX 6200 Systems Bhagyam Moses and Karen T. DeGregory 7 9 Overview of the Micro VAX 3500/3600 Processor Module Gary P. Lidington 87 Design of the MicroVAX 3500/3600 Second-level Cache Charles J. DeVane 95 The CVM 78034 Chip, a 32-bit Second-generation VAX Microprocessor Thomas F. Fox, Paul E. Gronowski, Anil K. Jain, Burton M. Leary, and Daniel G. Miner 109 Development of the CVAX Floating Point Chip Edward J. McLellan, Gilbert M. Wolrich, and Robert AJ Yodlowski 12 1 The System Support Chip, a Multifunction Chip for CVAX Systems Jeff Winston 129 Developmertt of the CVAX 922-bus Interface Chip Barry A. Maskas 1 39 The CVAX CMCTL - A CMOS Memory Controller Chip David K. Morgan Editor's introduction In the last paper related to the VAX 6200 system, Rhagyam Moscs and Karen DeGregory describe the development of workloads to measure VAX 6240 performance. As part of their discussion, they include performance measurements and analysis. The second new system based on the CVAX chip set is the low-end MicroVAX 3500/3600 system, which offers three times the performance of its predecessor, the MicroVAX 11. In his over- view of the major sections of the processor mod- ule, Gary Lidington relates how schedule and performance requirements influenced product C. Jane Blake design decisions. Editor Charles DeVane then describes the MicroVAX 3 500/3600 system's two-level cache architecture, The second issue of the Digital TecbnicalJournul with cmphasis on the design of the second-level (March 1986) feat~lred papers on the then cache. He also presents some cache performance recently announced MicroVAX 11 system, a system test results. based on a single-chip VAX implementation. In The high perforn~anceof both the VAX 6200 this seventh issue, we present papers on the sec- family and the MicroVAX 3500/3600 system is ond generation of that chip set, CVAX, the two attributable in great measure to the CMOS VAX new systems that take advantage of its increased family of chips on which these systems are based. performance capabilities, and a new version of Our five final papers address the design and the VAX/VMS operating system for symmetric development of this chip set. Frank Fox, Paul multiprocessing. Gronowski, Anil Jain, Mike Leary, and Dan Miner The new mid-range system based on the CVAX begin the discussion with an explanation of how chip set is the VAX 6200 family of computers, designers achieved the performance goals for the which utilizes a multiprocessing architecture. single-chip VAX CPU by reducing ticks per The first of two papers by Brian Allison is an instruction and machine cycle time. overview of this highly configurable, expandable A companion to the CVAX CPU, the floating system. Brian's second paper offers insights into point processor chip offers floating point perfor- the architectural definition process for the 6200. mance equal to that of the microprocessor for One of the major decisions made by the 6200 integer operations. The approach taken to attain engineers was to design a new interconnect to this goal and a description of the chip are pre- support the multiprocessor system. Rick Gillett sented by Ed McLellan, Gil Wolrich, and Bob presents an informative discussion of the com- Yodlowski. plexities involved in interfacing a microprocessor Jeff Winston then discusses the development of to a high-speed, multiprocessing bus. the system support chip, which provides a com- To ensure the availability of first-pass func- mon core of peripheral system functions. tional parts, a design verification team of engi- Next, Barry Maskas relates the design efforts of neers worked in parallel with the 6200 module three groups, one in Japan and two in the U.S., designers. Jean Basmaji, Glenn Ga~ey,Masood that resulted in a single-chip interface between Heydari, anti Art Singer discuss the computcr- the CVAX microprocessor and the Q22-bus 1/0 aided engineering and verification principles the subsystem. team instituted for the project. In our final paper, Dave Morgan describes the Rod Gamache and Kathy Morse then describe CVAX memory controller chip, CMCTL, which is the major features of synlmetric multiprocessing optimized for Q-bus-based systems. in the VAX/VMS operating system. Of particular interest is their description of a new synchroniza- tion method implelnented in VAX/VMS version 5 .O. Biographies Brian R. Allison Brian Allison, a consultant engincer for mid-range VAX systems, was the system architect responsible for the coordination of the VAX 6200 system definition and design. Prior to this work, he served as system architect for a project that yiclded several products. including DEBNA, DEBNK, and the KA800. As a member of the VAX-11/750 design team, he wrote various portions of the microcode for that product. Brian holds a B.S.E.E. and a B.S.C.S. from Worcester Polytechnic Institute (1977). Jean H. Basmaji Jean Basmaji is the technical director of computer-aided engineering and design-verification testing for the VAX 6200 project. A soft- ware consultant engineer, he has also been involved with CAE/DVT planning and scheduling, and has served as CAE/DVT project leader for the VAX 6200 CPU module. Jean joined Digital after receiving his B.S.E E from Lowell Technological Institute in 1077. Karen T. DeGregory A scnior software engineer in the Systems Perfor- mance Analysis Group, Karen DeGregoly is project leader of systems perfor- mance measurement for the \'AX 8840 and VAX 6240 systems. In addition to planning and implementing the measurements, she helped develop appro- priate workloads for these systems. Prior to this work, Karen was a senior software specialist in the Softwarc Services Backup Support Group. She reccived her B.S. (1980) with honors and distinction and her M.S. (1 98 1) m4 from Cornell University. Charles J. DeVane Charles DcVane is a scnior hardware engineer in the MicroVAX Systems Development Group. For the MicroVAX 3500/3600 pro- ject, he designed the second-level cache on the KA650 CPU module and guidcd the process of module system debug and introduction to manufactur- ing. Before joining Digital in 1981, Charles received a B.S.E.E. from North Carolina State University in Raleigh, North carol in;^. He is a mcrnber of Eta Kappa Nu and Tau Beta Pi engineering honor societies. Biographies Thomas F. Fox Frank Fox, a principal cngineer in the Semiconductor Engi- ncering Group, workcd on the implementation of the CVAX 78034 CPU chip. He is currently designing a high-performance microprocessor and consulting with the Adv;lnced Semiconductor Development Group on the development of a sub~nicronCMOS proccss.