Universal Verification Methodology (UVM) 1.2 User’s Guide October 8, 2015 Copyright © 2011 - 2015 Accellera. All rights reserved. October 8, 2015 UVM 1.2 User’s Guide Copyright© 2011 - 2015 Accellera Systems Initiative (Accellera). All rights reserved. Accellera Systems Initiative, 8698 Elk Grove Bldv Suite 1, #114, Elk Grove, CA 95624, USA Copyright© 2013 - 2015 Advanced Micro Devices, Inc. All rights reserved. Advanced Micro Devices (AMD), 7171 Southwest Parkway, Austin, TX 78735 Copyright© 2011 - 2015 Cadence Design Systems, Inc. (Cadence). All rights reserved. Cadence Design Systems, Inc., 2655 Seely Ave., San Jose, CA 95134, USA. Copyright© 2011 - 2015 Mentor Graphics, Corp. (Mentor). All rights reserved. Mentor Graphics, Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA Copyright© 2013 - 2015 NVIDIA CORPORATION. All rights reserved. NVIDIA Corporation, 2701 San Tomas Expy, Santa Clara, CA 95050 Copyright© 2011 - 2015 Synopsys, Inc. (Synopsys). All rights reserved. Synopsys, Inc., 690 E. Middlefield Rd, Mountain View, CA 94043 This product is licensed under the Apache Software Foundation’s Apache License, Version 2.0, January 2004. The full license is available at: http://www.apache.org/licenses/. Notices While this guide offers a set of instructions to perform one or more specific verification tasks, it should be supplemented by education, experience, and professional judgment. Not all aspects of this guide may be applicable in all circumstances. The UVM 1.2 User’s Guide does not necessarily represent the standard of care by which the adequacy of a given professional service must be judged nor should this document be applied without consideration of a project’s unique aspects. This guide has been approved through the Accellera consensus process and serves to increase the awareness of information and approaches in verification methodology. This guide may have several recommendations to accomplish the same thing and may require some judgment to determine the best course of action. The UVM 1.2 Class Reference represents the foundation used to create the UVM 1.2 User’s Guide. This guide is a way to apply the UVM 1.2 Class Reference, but is not the only way. Accellera believes standards are an important ingredient to foster innovation and continues to encourage industry innovation based on its standards. Suggestions for improvements to the UVM 1.2 User’s Guide are welcome. They should be sent to the UVM email reflector [email protected] ii Copyright © 2011 - 2015 Accellera. All rights reserved. UVM 1.2 User’s Guide October 8, 2015 Contents 1. Overview.............................................................................................................................................. 1 1.1 The Typical UVM Testbench Architecture................................................................................ 1 1.1.1 UVM Testbench .......................................................................................................... 2 1.1.2 UVM Test ................................................................................................................... 2 1.1.3 UVM Environment ..................................................................................................... 2 1.1.4 UVM Scoreboard ........................................................................................................ 2 1.1.5 UVM Agent ................................................................................................................2 1.1.6 UVM Sequencer ......................................................................................................... 3 1.1.7 UVM Sequence ........................................................................................................... 3 1.1.8 UVM Driver ................................................................................................................ 3 1.1.9 UVM Monitor ............................................................................................................. 4 1.2 The UVM Class Library............................................................................................................. 4 2. Transaction-Level Modeling (TLM) ................................................................................................... 7 2.1 Overview .................................................................................................................................... 7 2.2 TLM, TLM-1, and TLM-2.0 ...................................................................................................... 7 2.3 TLM-1 Implementation.............................................................................................................. 8 2.3.1 Basics .......................................................................................................................... 8 2.3.2 Encapsulation and Hierarchy .................................................................................... 12 2.3.3 Analysis Communication .......................................................................................... 14 2.4 TLM-2.0 Implementation......................................................................................................... 16 2.4.1 Generic Payload ........................................................................................................ 16 2.4.2 Core Interfaces and Ports .......................................................................................... 19 2.4.3 Blocking Transport ................................................................................................... 20 2.4.4 Nonblocking Transport ............................................................................................. 20 2.4.5 Sockets ...................................................................................................................... 22 2.4.6 Time .......................................................................................................................... 25 2.4.7 Use Models ...............................................................................................................27 3. Developing Reusable Verification Components................................................................................ 29 3.1 Modeling Data Items for Generation ....................................................................................... 29 3.1.1 Inheritance and Constraint Layering ......................................................................... 30 3.1.2 Defining Control Fields (“Knobs”) ........................................................................... 31 3.2 Transaction-Level Components ............................................................................................... 32 3.3 Creating the Driver................................................................................................................... 34 3.4 Creating the Sequencer............................................................................................................. 35 3.5 Connecting the Driver and Sequencer..................................................................................... 35 3.5.1 Basic Sequencer and Driver Interaction ................................................................... 36 3.5.2 Querying for the Randomized Item .......................................................................... 36 3.5.3 Fetching Consecutive Randomized Items ................................................................. 37 3.5.4 Sending Processed Data back to the Sequencer ........................................................ 37 3.5.5 Using TLM-Based Drivers ....................................................................................... 38 3.6 Creating the Monitor ................................................................................................................ 38 3.7 Instantiating Components......................................................................................................... 40 3.8 Creating the Agent ................................................................................................................... 41 3.8.1 Operating Modes ....................................................................................................... 41 3.8.2 Connecting Components ........................................................................................... 43 Copyright © 2011 - 2015 Accellera. All rights reserved. iii October 8, 2015 UVM 1.2 User’s Guide 3.9 Creating the Environment ........................................................................................................ 43 3.9.1 The Environment Class ............................................................................................. 43 3.9.2 Invoking build_phase ................................................................................................ 44 3.10 Enabling Scenario Creation...................................................................................................... 44 3.10.1 Declaring User-Defined Sequences .......................................................................... 45 3.10.2 Sending Subsequences and Sequence Items ............................................................. 45 3.10.3 Starting a Sequence on a Sequencer ......................................................................... 48 3.10.4 Overriding Sequence Items and Sequences .............................................................. 49 3.11 Managing End of Test.............................................................................................................