www.ti.com Table of Contents User’s Guide MSP430™ Programming With the JTAG Interface ABSTRACT This document describes the functions that are required to erase, program, and verify the memory module of the MSP430™ flash-based and FRAM-based microcontroller families using the JTAG communication port. Table of Contents 1 Introduction.............................................................................................................................................................................3 1.1 About This Document.........................................................................................................................................................3 1.2 Organization of This Document..........................................................................................................................................3 2 Programming Using the JTAG Interface...............................................................................................................................4 2.1 Introduction........................................................................................................................................................................ 4 2.1.1 MSP430 JTAG Restrictions (Noncompliance With IEEE Std 1149.1)......................................................................... 4 2.1.2 TAP Controller State Machine..................................................................................................................................... 4 2.2 Interface and Instructions...................................................................................................................................................4 2.2.1 JTAG Interface Signals................................................................................................................................................5 2.2.2 JTAG Access Macros.................................................................................................................................................. 6 2.2.3 Spy-Bi-Wire (SBW) Timing and Control.......................................................................................................................9 2.2.4 JTAG Communication Instructions............................................................................................................................ 14 2.3 Memory Programming Control Sequences...................................................................................................................... 20 2.3.1 Start-Up..................................................................................................................................................................... 20 2.3.2 General Device (CPU) Control Functions..................................................................................................................23 2.3.3 Accessing Non-Flash Memory Locations With JTAG................................................................................................ 33 2.3.4 Programming the Flash Memory (Using the Onboard Flash Controller)................................................................... 37 2.3.5 Erasing the Flash Memory (Using the Onboard Flash Controller).............................................................................42 2.3.6 Reading From Flash Memory.................................................................................................................................... 45 2.3.7 Verifying the Target Memory......................................................................................................................................45 2.3.8 FRAM Memory Technology....................................................................................................................................... 48 2.4 JTAG Access Protection...................................................................................................................................................48 2.4.1 Burning the JTAG Fuse - Function Reference for 1xx, 2xx, 4xx Families................................................................. 50 2.4.2 Programming the JTAG Lock Key - Function Reference for 5xx, 6xx, and FRxx Families........................................52 2.4.3 Testing for a Successfully Protected Device..............................................................................................................53 2.4.4 Unlocking an FRAM Device in Protected and Secured Modes................................................................................. 54 2.4.5 Memory Protection Unit Handling..............................................................................................................................54 2.4.6 Intellectual Property Encapsulation (IPE).................................................................................................................. 55 2.4.7 FRAM Write Protection..............................................................................................................................................55 2.5 JTAG Function Prototypes............................................................................................................................................... 56 2.5.1 Low-Level JTAG Functions........................................................................................................................................56 2.5.2 High-Level JTAG Routines........................................................................................................................................ 58 2.6 JTAG Features Across Device Families...........................................................................................................................63 2.7 References.......................................................................................................................................................................73 3 JTAG Programming Hardware and Software Implementation..........................................................................................74 3.1 Implementation History.................................................................................................................................................... 74 3.2 Implementation Overview.................................................................................................................................................74 3.3 Software Operation.......................................................................................................................................................... 74 3.4 Software Structure........................................................................................................................................................... 75 3.4.1 Programmer Firmware...............................................................................................................................................75 3.4.2 Target Code............................................................................................................................................................... 76 3.5 Hardware Setup............................................................................................................................................................... 77 3.5.1 Host Controller...........................................................................................................................................................78 3.5.2 Target Connection..................................................................................................................................................... 78 3.5.3 Host Controller or Programmer Power Supply.......................................................................................................... 79 SLAU320AJ – JULY 2010 – REVISED MAY 2021 MSP430™ Programming With the JTAG Interface 1 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Trademarks www.ti.com 3.5.4 Third-Party Support................................................................................................................................................... 80 4 Errata and Revision Information......................................................................................................................................... 81 4.1 Known Issues...................................................................................................................................................................81 4.2 Revisions and Errata From Previous Documents............................................................................................................ 81 5 Revision History................................................................................................................................................................... 82 Trademarks MSP430™ and Code Composer Studio™ are trademarks of Texas Instruments. IAR Embedded Workbench® is a registered trademark of IAR Systems. All trademarks are the property of their respective owners. 2 MSP430™ Programming With the JTAG Interface SLAU320AJ – JULY 2010 – REVISED MAY 2021 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated www.ti.com Introduction 1 Introduction 1.1 About This Document This document describes the functions that are required to erase, program, and verify the memory module of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition, it describes how to program the