The PowerPC Compiler Writer’s Guide Edited by: Steve Hoxey Faraydon Karim Bill Hay Hank Warren Warthman Associates © International Business Machines Corporation 1996. All rights reserved. 1-96. Printed in the United State of America. This notice applies to The PowerPC Compiler Writer’s Guide, dated January 1996. The following paragraphs do not apply in any country or state where such provisions are inconsistent with local law: The specifications in this publication are subject to change without notice. The publication is provided “AS IS.” International Business Machines Corporation (hereafter “IBM”) does not make any warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. 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IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6531 Tel: (800) POWERPC Fax Service 415-855-4121 The IBM home page can be found at: http://www.ibm.com The IBM Microelectronics Division PowerPC home page can be found at: http://www.chips.ibm.com/products/ppc Library of Congress Catalog Card Number: 95-62115 ISBN 0-9649654-0-2 Published for IBM by: Warthman Associates 240 Hamilton Avenue Palo Alto, California 94301 (415) 322-4555 [email protected] Foreword By Fredrick R. Sporck Director IBM Microelectronics Division—PowerPC Products IBM’s reputation for commitment to technology and innovation is legendary in the computer industry. Over the past two decades, IBM has followed this tradition with its dedication to the development and enhancement of RISC architecture. With the introduction of the PowerPC architecture, IBM has again recognized the need for supporting its products. In response, IBM has prepared The PowerPC Compiler Writer’s Guide. Some of the brightest minds from many companies in the fields of compiler and pro- cessor development have combined their efforts in this work. A balanced, insightful exami- nation of the PowerPC architecture and the pipelines implemented by PowerPC processors has yielded a guide giving compiler developers valuable insight into the generation of high- performance code for PowerPC processors. By taking this step, IBM is equipping readers of The PowerPC Compiler Writer’s Guide with the power to harness the potential of the PowerPC revolution. Once again, IBM is stepping forward with dedication to its customers and the powerful backing of its cutting-edge archi- tecture. Contents 1. Introduction 1 1.1 RISC Technologies........................................................................................................ 1 1.2 Compilers and Optimization .......................................................................................... 3 1.3 Assumptions................................................................................................................. 4 2. Overview of the PowerPC Architecture 5 2.1 Application Environment ............................................................................................... 5 2.1.1 32-Bit and 64-Bit Implementations and Modes......................................................... 5 2.1.2 Register Resources................................................................................................... 7 2.1.2.1 Branch.................................................................................................................. 7 2.1.2.2 Fixed-Point ........................................................................................................... 7 2.1.2.3 Floating-Point....................................................................................................... 8 2.1.3 Memory Models........................................................................................................ 8 2.1.3.1 Memory Addressing ............................................................................................. 8 2.1.3.2 Endian Orientation.............................................................................................. 10 2.1.3.3 Alignment........................................................................................................... 10 2.1.4 Floating-Point ......................................................................................................... 11 2.2 Instruction Set ............................................................................................................ 13 2.2.1 Optional Instructions .............................................................................................. 13 2.2.2 Preferred Instruction Forms.................................................................................... 14 2.2.3 Communication Between Functional Classes.......................................................... 14 2.2.3.1 Fixed-Point and Branch Resources..................................................................... 14 2.2.3.2 Fixed-Point and Floating-Point Resources.......................................................... 15 2.2.3.3 Floating-Point and Branch Resources ................................................................ 15 3. Code Selection 17 3.1 Control Flow................................................................................................................ 17 3.1.1 Architectural Summary ........................................................................................... 19 3.1.1.1 Link Register ...................................................................................................... 19 3.1.1.2 Count Register.................................................................................................... 20 3.1.1.3 Condition Register.............................................................................................. 21 3.1.2 Branch Instruction Performance............................................................................. 22 3.1.2.1 Fall-Through Path............................................................................................... 23 3.1.2.2 Needless Branch Register and Recording Activity .............................................. 23 3.1.2.3 Condition Register Contention............................................................................ 23 3.1.3 Uses of Branching .................................................................................................. 23 3.1.3.1 Unconditional Branches...................................................................................... 23 v 3.1.3.2 Conditional Branches..........................................................................................24 3.1.3.3 Multi-Way Conditional Branches.........................................................................25 3.1.3.4 Iteration ..............................................................................................................28 3.1.3.5 Procedure Calls and Returns ..............................................................................32 3.1.3.6 Traps and System Calls ......................................................................................34 3.1.4 Branch Prediction ...................................................................................................35 3.1.4.1 Default Prediction and Rationale.........................................................................35 3.1.4.2 Overriding Default Prediction..............................................................................36 3.1.4.3 Dynamic Branch Prediction ................................................................................37 3.1.5 Avoiding Branches ..................................................................................................37