The Design and Testing of a Superconducting Programmable Gate Array by Hein van Heerden Thesis presented at the University of Stellenbosch in partial fulfilment of the requirements for the degree of Master of Science in Electronic Engineering Department of Electrical and Electronic Engineering University of Stellenbosch Private Bag X1, 7602 Matieland, South Africa Study leader: Dr. C.J. Fourie December 2005 Copyright © 2005 University of Stellenbosch All rights reserved. Declaration I, the undersigned, hereby declare that the work contained in this thesis is my own original work and that I have not previously in its entirety or in part submitted it at any university for a degree. Signature: . H. van Heerden Date: . ii Abstract This thesis investigates to the design, analysis and testing of a Superconducting Programmable Gate Array (SPGA). The objective was to apply existing programmable logic concepts to RSFQ circuits and in the process develop a working prototype of a superconducting pro- grammable logic device. Various programmable logic technologies and architectures were examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ) circuits as building blocks, a complete functional design was assembled incorporating a rout- ing architecture and logic blocks. The Large-Scale Integrated circuit (LSI) layout of the final chip is presented and discussed followed by a discussion on testing. This thesis demon- strates the successful implementation of a fully functional reprogrammable logic device us- ing RSFQ circuitry. iii Opsomming Hierdie tesis handel oor die ontwerp, analise en toets van 'n SPGA (Superconducting Pro- grammable Gate Array). Die doel is om huidige programeerbare logika konsepte aan te pas en in die proses 'n werkende prototipe te ontwikkel wat beskryf kan word as 'n supergeleier programeerbare logiese toestel wat se werking soortgelyk is aan dié van FPGAs. 'n Verskei- denheid van programeerbare logika tegnologieë en argitekture is ondersoek en met mekaar vergelyk om die beste oplossing te vind. Met RSFQ (Rapid Single Flux Quantum) stroom- bane as boublokke is 'n hele funksionele ontwerp aanmekaar gesit wat beide 'n verspreid- ingsargitektuur en logieseblokke inkorporeer. Die grootskaalse geïntegreerde stroombaan uitleg van die finale vlokkie word bespreek en voorgelê. Daarna volg 'n bespeking oor toetsing van die ontwerp. Hierdie tesis demonstreer die suksesvolle implementering van 'n werkende herprogrameerbare logika toestel bestaande uit RSFQ stroombane. iv Acknowledgements I would like to express my sincere gratitude to the following people and organisations who have contributed to making this work possible: • Steve R. Whiteley for his invaluable simulation tools, which made this project feasible. • Hypres Inc. for providing the fabrication platform on which the physical implementa- tion of this project is based. Especially Dr. S. Tolpygo, head of fabrication, for his help and direction. • The National Research Foundation of South Africa (and Prof. D.B. Davidson as grantholder) for providing some financial assistance during my research. • My fellow students and good friends, Hennie de Villiers and Wynand van Staden for providing inspiration and support during difficult times. • Prof. Willem J. Perold for giving me the inspiration and opportunity to pursue my quest for further enrichment in the field of engineering. Also, for his eternal optimism and enthusiasm. • Lastly, but most of all, Dr. Coenrad J. Fourie as my study leader for the countless hours of advice and guidance and also for providing me with a good background and basis on which to build this project. v Dedications This thesis is dedicated to my mother for her support, encouragement and eternal love. Sadly, she passed away before the completion of this project. She will be missed. vi Contents Declaration ii Abstract iii Opsomming iv Acknowledgements v Dedications vi Contents vii List of Figures xi List of Tables xiv Nomenclature xv 1 Introduction 1 1.1 Semiconductor programmable logic . 1 1.2 Superconducting logic . 1 1.3 SPGA . 2 1.4 Summary of thesis . 2 2 SPGA background and RSFQ basics 3 2.1 SPGA background . 3 2.2 RSFQ basics . 4 3 Programmable logic 7 3.1 Field-programmable gate array . 7 3.1.1 Architectures . 7 3.1.2 Programming technologies . 9 3.1.3 Implementation . 11 vii CONTENTS viii 3.2 Technology mapping . 16 3.2.1 Lookup table mapping . 16 3.2.2 Multiplexer mapping . 17 3.2.3 Examples . 17 3.3 Area vs Functionality . 24 3.3.1 Model . 24 3.3.2 Logic block area and routing model . 24 3.3.3 Area vs. functionality experiment . 25 3.4 SPGA . 28 3.5 Chapter summary . 29 4 SPGA design 30 4.1 Basic gates . 30 4.1.1 DCRL . 30 4.1.2 HUFFLE . 32 4.1.3 I-Switch . 34 4.1.4 I2-Switch . 35 4.1.5 MSL Driver and Receiver pair . 36 4.1.6 RSFQ-to-COSL Converter . 38 4.2 Monte Carlo analysis and simulations . 39 4.3 Inductance restrictions between gates . 39 4.4 Composite blocks . 40 4.4.1 Inline Switch . 40 4.4.2 Junction Switch . 40 4.4.3 Crossbar Switch . 42 4.4.4 Logic Block . 43 4.4.5 Programming Frame . 47 4.5 SPGA . 50 4.6 Functional Verilog simulation of the SPGA . 51 4.6.1 Functional models . 51 4.6.2 Programming and simulation . 56 4.7 Chapter summary . 62 5 Physical layout 63 5.1 Hierarchical layout design approach . 65 5.2 Basic gates . 65 5.2.1 AND gate . 66 5.2.2 DCRL . 66 5.2.3 I2-Switch . 67 CONTENTS ix 5.3 Microstrip transmission lines . 70 5.4 Composite blocks . 71 5.4.1 Logic Block . 72 5.4.2 Programming Logic Column driver . 73 5.4.3 Programming Logic Row driver . 74 5.4.4 Full chip layout . 75 5.5 Error checking and verification . 76 5.5.1 Gate verification . 76 5.5.2 Signal route checking . 76 5.5.3 Connection checking . 81 5.5.4 Design rule checking . 82 5.5.5 Full-chip scan . 83 5.6 Parameter extraction . 83 5.6.1 SLine . 83 5.6.2 FastHenry and InductEx . 83 5.6.3 Example: I2-Switch . 84 5.7 Input and output impedance matching . 85 5.8 Signal-to-Pad assignments . 85 5.9 Moats . 89 5.10 Chapter summary and conclusions . 89 6 Testing 91 6.1 Testbed . 91 6.1.1 Cryocooler . 92 6.1.2 Room temperature electronics . 95 6.2 Test cases . 96 6.2.1 Example 1: Direct input to output . 98 6.2.2 Example 2: One logic block . 98 6.2.3 Example 3: Comprehensive logic function . 100 6.3 Test results . 102 7 Conclusions and recommendations 105 List of References 107 Appendices 112 A Verilog modules 113 A.1 SM1 . 113 A.2 SM_STOP . 113 CONTENTS x A.3 LUT_IN . 114 A.4 LUT_OUT . 115 A.5 LB . 115 A.6 SPGA . 116 B Spice code 119 B.1.