Asynchronous System-on-Chip Interconnect A thesis submitted to the University of Manchester for the degree of Doctor of Philosophy in the Faculty of Science & Engineering March 2000 William John Bainbridge Department of Computer Science 1 Contents Contents ...................................................................................................................2 List of Figures .........................................................................................................6 List of Tables ...........................................................................................................8 Abstract ...................................................................................................................9 Declaration ............................................................................................................10 Copyright ...............................................................................................................10 The Author ............................................................................................................11 Acknowledgements ...............................................................................................12 Chapter 1: Introduction ....................................................................................13 1.1 Asynchronous design and its advantages ...............................................14 1.1.1 Avoidance of clock-skew .............................................................15 1.1.2 Low power ...................................................................................15 1.1.3 Improved electro-magnetic compatibility (EMC) ........................16 1.1.4 Modularity ....................................................................................16 1.1.5 Better than worst-case performance .............................................17 1.2 Disadvantages of asynchronous design ..................................................18 1.2.1 Complexity ...................................................................................18 1.2.2 Deadlock ......................................................................................18 1.2.3 Verification ..................................................................................18 1.2.4 Testability .....................................................................................19 1.2.5 “It’s not synchronous” .................................................................19 1.3 Thesis Overview .....................................................................................19 1.4 Publications ............................................................................................22 Chapter 2: Asynchronous Design .....................................................................23 2.1 Introduction ............................................................................................23 2.2 Asynchronous design ..............................................................................25 2.2.1 Circuit classification ....................................................................25 2.2.2 The channel ..................................................................................26 2.2.3 Signalling conventions .................................................................27 2.2.4 Data representation ......................................................................29 2.2.5 The Muller C-element ..................................................................32 2.2.6 Specifications and automated circuit synthesis ............................32 2.2.7 Metastability, arbitration and synchronisation .............................35 2.2.8 Sutherland’s micropipelines .........................................................36 2.2.9 Large Asynchronous Circuits .......................................................38 2.3 Summary .................................................................................................40 Chapter 3: System Level Interconnect Principles ...........................................41 3.1 Point-to-point communication paths ......................................................41 3.2 Multipoint interconnect topology ...........................................................42 3.2.1 Shared buses .................................................................................42 3.2.2 Star and Ring Networks ...............................................................42 3.2.3 Meshes .........................................................................................42 3.3 Bus protocol issues .................................................................................43 2 3.3.1 Serial operation ............................................................................44 3.3.2 Multiplexed address/data lines .....................................................44 3.3.3 Separate address and data lines ....................................................44 3.3.4 Arbitration ....................................................................................45 3.3.5 Atomic sequences ........................................................................46 3.3.6 Bursts ...........................................................................................46 3.3.7 Interlocked or decoupled transfers ...............................................46 3.3.8 Split transactions ..........................................................................46 3.4 Interconnect performance objectives ......................................................47 3.5 Commercial on-chip buses .....................................................................47 3.5.1 Peripheral Interconnect Bus (PI-Bus) ..........................................48 3.5.2 The Advanced Microcontroller Bus Architecture (AMBA) ........48 3.5.3 CoreConnect .................................................................................49 3.6 Summary .................................................................................................51 Chapter 4: The Physical (Wire) Layer .............................................................52 4.1 Wire theory .............................................................................................53 4.2 Electrical and physical characteristics ....................................................54 4.3 Termination ............................................................................................55 4.4 Crosstalk .................................................................................................55 4.4.1 Propagation delay for well separated wires .................................58 4.4.2 Signal propagation delay with close-packed wires ......................58 4.4.3 Alternative wiring arrangements ..................................................59 4.5 Summary .................................................................................................64 Chapter 5: The Link Layer ...............................................................................65 5.1 Centralised vs distributed interfaces .......................................................66 5.2 Signalling Convention ............................................................................67 5.3 Data Encoding ........................................................................................67 5.4 Handshake sources .................................................................................68 5.5 Bidirectional data transfer ......................................................................69 5.6 Multiple initiators on one channel ..........................................................70 5.6.1 Arbitration ....................................................................................71 5.6.2 Request drive and hand-over ........................................................77 5.6.3 Push data drive and hand-over .....................................................78 5.6.4 Transfer deferral/hardware retry ..................................................79 5.6.5 Atomic transfers and locking .......................................................81 5.7 Multiple Targets .....................................................................................83 5.7.1 Acknowledge drive and hand-over ..............................................83 5.7.2 Target selection ............................................................................84 5.7.3 Decode and target exceptions ......................................................85 5.7.4 Pull data drive and hand-over ......................................................85 5.7.5 Defer .............................................................................................86 5.8 Multipoint bus-channel interfaces ..........................................................86 5.9 MARBLE’s Link Layer Channels ..........................................................88 5.10 Summary ...............................................................................................89 Chapter 6: Protocol Layer .................................................................................90 6.1 Transfer phases .......................................................................................91 6.1.1 The command phase .....................................................................91 3 6.1.2 The acknowledge phase ...............................................................92 6.1.3 The data phase ..............................................................................92 6.1.4