1GB (x72, ECC, PLL) 200-PIN DDR SODIMM PC3200 Features Small-Outline DDR SDRAM DIMM MT18VDDT12872PH(I) – 1GB For the latest data sheet, please refer to the MicronWeb site: www.micron.com/module. Features Figure 1: 200-Pin SODIMM (MO-224) • 200-pin, small-outline, dual in-line memory Height 1.25in. (31.75mm) module (SODIMM) • Supports ECC error detection and correction • Fast data transfer rate: PC3200 • Utilizes 267 MT/s and 333 MT/s DDR SDRAM components • 1GB (128 Meg x 72, stacked) •VDD = VDDQ = +2.6V •VDDSPD = +2.3V to +3.6V • 2.5V I/O (SSTL_2 compatible) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; center- aligned with data for WRITEs Options Marking • Internal, pipelined double data rate (DDR) • Operating Temperature Range architecture; two data accesses per clock cycle Commercial (0°C T +70°C) None • Bidirectional data strobe (DQS) transmitted/re- A Industrial (-40°C T +85°C) I2 ceived with data—i.e., source-synchronous data A •Package capture 200-pin SODIMM (standard) G • Differential clock inputs CK and CK# 200-pin SODIMM (lead-free) Y • Four internal device banks for concurrent operation • Clock Frequency/CAS Latency • Programmable burst lengths: 2, 4, or 8 200 MHz (400 MT/s) CL = 31 -40B • Auto precharge option •PCB Height • Auto Refresh and Self Refresh Modes Standard 1.25in. (31.75mm) • 7.8125µs maximum average periodic refresh interval Notes: 1. CL = Device CAS (READ) Latency. • Serial Presence Detect (SPD) with EEPROM 2. Consult Micron for product availability. • Programmable READ CAS latency • Gold edge contacts pdf: 09005aef81697898/source: 09005aef8169786e Micron Technology, Inc., reserves the right to change products or specifications without notice. DDA18C128x72PH_1.fm - Rev. B 10/13 EN 1 ©2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1GB (x72, ECC, PLL) 200-PIN DDR SODIMM PC3200 Features Table 1: Address Table 1GB Refresh Count 8K Row Addressing 8K (A0–A12) Device Bank Addressing 4 (BA0, BA1) Base Device Configuration 512Mb (64 Meg x 8) Column Addressing 2K (A0–A9, A11) Module Rank Addressing 2 (S0#, S1#) Table 2: Part Numbers and Timing Parameters Part Number Module Module Memory Clock/ Clock Latency Density Configuration Bandwidth Data Rate (CL - tRCD - tRP) MT18VDDT12872PHG-40B__ 1GB 128 Meg x 72 3.2 GB/s 5.4ns/400 MT/s 3-3-3 MT18VDDT12872PHY-40B__ 1GB 128 Meg x 72 3.2 GB/s 5.4ns/400 MT/s 3-3-3 All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDT12872PHG-335A1. pdf: 09005aef81697898/source: 09005aef8169786e Micron Technology, Inc., reserves the right to change products or specifications without notice. DDA18C128x72PH_1.fm - Rev. B 10/13 EN 2 ©2004 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, PLL) 200-PIN DDR SDRAM SODIMM Table of Contents Table of Contents Features. .1 Table of Contents . .3 List of Figures . .4 List of Tables. .5 Pin Assignments and Descriptions . .6 Functional Block Diagram. .9 General Description . .10 PLL Operation . .10 Serial Presence-Detect Operation . .10 Mode Register Definition . .11 Burst Length . .11 Burst Type . .11 Read Latency . .12 Operating Mode . .14 Extended Mode Register . .15 DLL Enable/Disable. .15 Commands . .16 Absolute Maximum Ratings . .17 Electrical Specifications. .17 Notes . .21 Initialization . .25 PLL Specifications. .27 Thermal Specifications . .28 Serial Presnce-Detect . .29 SPD Clock and Data Conventions . .29 SPD Start Condition. .29 SPD Stop Condition . .29 SPD Acknowledge. .29 Package Dimensions . .35 Data Sheet Designation . .35 Revision History. .36 pdf: 09005aef81697898/source: 09005aef8169786e Micron Technology, Inc., reserves the right to change products or specifications without notice. DDA18C128x72PHTOC.fm - Rev. B 10/13 EN 3 ©2004 Micron Technology, Inc. All rights reserved. 1GB (x72, ECC, PLL) 200-PIN DDR SDRAM SODIMM List of Figures List of Figures Figure 1: 200-Pin SODIMM (MO-224) . .1 Figure 2: Module Layout . .6 Figure 3: Functional Block Diagram . .9 Figure 4: Mode Register Definition Diagram . .12 Figure 5: CAS Latency Diagram . .14 Figure 6: Extended Mode Register Definition Diagram . .15 Figure 7: Pull-Down Characteristics . .23 Figure 8: Pull-Up Characteristics . ..