294 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 3, MARCH 2001 Differential Signaling with a Reduced Number of Signal Paths Anthony Carusone, Kamran Farzan, and David A. Johns Abstract—Differential signaling is often used for digital chip-to-chip in- terconnects because it provides common-mode noise rejection. Unfortu- nately, differential signals generally require 2 signal paths to commu- nicate signals. In this paper, a method for differential signaling is de- scribed that requires as few as C1 signal paths for signals. Using this method, the signal values appear incrementally between neighboring matched signal paths. The technique, called incremental signaling, is sim- ilar to dicode (1 ) partial response signaling except that the sequence is transmitted in parallel over a bus of wires rather than sequentially in time. Theoretical and simulated bit error rates are presented for several possible implementations of an encoder/transmitter and receiver/decoder for a dig- ital data bus including peak detection and maximum likelihood sequence detection (MLSD). Peak detection uses C1 signal paths and results in a 3-dB performance degradation with respect to independent noise com- pared with fully differential signaling. The Viterbi algorithm for MLSD uses C2 signal paths but provides only a 1.25 dB improvement over peak detection due to correlated noise on the (1 )-coded sequence. Modified Viterbi algorithms that use C2 signal paths are introduced to cancel the correlated noise sources, resulting in a bit error rate performance compa- rable with fully differential signaling. Fig. 1. A practical single-ended signaling system or “pseudodifferential” Index Terms—Chip-to-chip interface, differential signaling, maximum signaling with additional reference lines added after every four signal paths. likelihood sequence detection. I. INTRODUCTION Recently, the noise margin on digital chip-to-chip interconnects has been decreasing for two main reasons. One reason is that supply volt- ages in digital CMOS processes are decreasing, thereby reducing the voltage available for driving I/Os. A second reason is that small signal swings are being used to reduce dynamic power dissipation on high- speed buses. It has long been known that fully differential signals ef- fectively reject common-mode noise and even-order distortion terms. Since common-mode noise is prevalent on matched PCB traces, differ- ential signaling is effective for both voltage [1], [2] and current-mode [3] digital chip-to-chip interfaces. Fully differential signals are now used in the scalable coherent interface [4], [5] and RamLink [6] stan- dards. Unfortunately, a practical problem with their implementation is that two signal paths are required for each signal. For example, using fully differential signals for a 64-bit data bus would require 128 pins on each IC package and 128 PCB trances routed between ICs. These Fig. 2. Block diagram of a fully differential signaling system for binary data. additional costs are often prohibitive. This paper describes a general technique for obtaining many of the cations to the Viterbi algorithm are described in Section V, which bring advantages of fully differential signals while using a reduced number the performance of MLSD close to that of fully differential signaling of signal paths. Specifically, x differential signals are communicated using only xC2 signal paths. Theoretical and simulated bit error rate over as few as xC1 signal paths. In Section II, the basic idea is de- (BER) results are presented for each approach on a digital data bus. As scribed. The technique is similar to partial response signaling except in partial response systems, the approaches are general and multilevel that the encoded sequence is transmitted in parallel over a set of wires signaling is possible. However, in this paper, results are only presented rather than sequentially in time over a serial connection. Possible im- for a binary data bus. Finally, a system that combines this approach plementations are then discussed. As in partial response systems, the with constant-weight digital encoding is proposed in Section VI. simplest approach is peak detection, which requires only xC1 signal paths and is discussed in Section III. Maximum likelihood sequence de- tection (MLSD) is another popular technique for partial response sys- II. INCREMENTAL SIGNALS tems. It uses xC2 signal paths and is discussed in Section IV. Modifi- In general, the problem is one of communicating x signals, xkY I k x, over w signal paths, ylY I l w. In a simple single-ended scheme, w a x and the receiver operates by comparing the signal on Manuscript received August 2000; revised February 2001. This paper was each path to reference threshold levels. Of course, the receiver is sus- recommended by Associate Editor M. Helfenstein. The authors are with the Department of Electrical and Computer Engineering, ceptible to common-mode noise on the bus. To combat this problem, University of Toronto, Toronto, ON M5S 1A4 Canada. practical single-ended systems often include reference signals trans- Publisher Item Identifier S 1057-7130(01)04202-1. mitted along the bus to provide some common-mode noise 1057–7130/01$10.00 © 2001 IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 3, MARCH 2001 295 Fig. 3. A general incremental signaling system. rejection. This approach has been referred to as “pseudodifferential” Fig. 4. Block diagram of a possible incremental signaling system for binary data using peak detection. signaling. For instance, a system with an extra reference line after every fourth active signal path is shown in Fig. 1. Of course, this increases TABLE I the pin count by 25%. Furthermore, there will always be some finite SIGNAL VALUES FOR THE PEAK DETECTION SYSTEM IN FIG.4WITH RANDOM common-mode-to-differential conversion due to mismatches between BINARY DATA OF WIDTH x a T AND NO NOISE signal paths along the bus. These mismatches can be minimized by comparing only neighboring signal paths. Using fully differential signals requires w a Px. The signals ap- pear as the difference between neighboring matched signal paths, as shown in Fig. 2 H H xk a yPk yPkIX (1) H where uk is the (possibly multilevel) information symbol being en- The primes in Fig. 2 and (1) denote noisy signals at the receiver, yk a coded and v is the number of signal levels to be transmitted on the bus. yk C nk. Note that (1) implies that we have complete freedom to ar- The receiver must then interpret the received signals modulo-v bitrarily select one-half of the signals levels.1 Clearly, there is some x x redundancy inherent in transmitting signals over 2 signal paths. uk a xk mod vX (5) This redundancy is eliminated by having the signals appear incremen- tally as the difference between adjacent signal paths The modular arithmetic in (4) and (5) has a particularly straightfor- ward hardware implementation when the uk are binary signals. The x a yH yH X k kCI k (2) modular addition in (4) can be performed by exclusive-OR gates Using this scheme, hereafter called incremental signaling, the sig- ykCI a yk ukX (6) nals still appear differentially between two adjacent wires, so all of the noise-rejection advantages of fully differential signals are obtained The modulo-v receiver can be just two differential comparators oper- using only w a x CIsignal paths. However, in (2), there is only ating as a peak detector. A system block diagram of this approach is freedom to fix one signal path value, namely, yI. shown in Fig. 4. Note that the precoder includes a cascade of x exclu- A completely general incremental signaling system is shown in sive-OR gates. However, it is possible to shorten the logic’s critical path Fig. 3. Several possible encoder/transmitter and receiver/decoder com- if it is limiting speed through the use of carry-lookahead or pipelining binations are possible, each offering a different compromise between techniques. Table I shows all of the signal values for a sample binary complexity and performance. Interpreting the received signals as the sequence of length x aTin the absence of noise. The receiver in H difference between adjacent signal path values as in (2) is analogous to Fig. 4 sees the noisy signals, yk a yk C nk. A bit error will occur H H applying the dicode @I hA partial response operator to a time series when independent noise on yk and ykCI causes the differential signal H H xk a ykCI yk to cross one of the slicer thresholds. If the bus signals x@kAay@kA y@k IAX (3) are members of a binary alphabet with spacing 2e, 'P is the variance of independent Gaussian noise on each yk, and a ea', then it can Therefore, popular approaches to encoding/transmitting and re- be shown that errors will occur with the following probability: ceiving/decoding partial response signals are also applicable here. Q I a p e P (7) III. PEAK DETECTION P To keep the receiver hardware as simple as possible, the information where @A is defined as bits can be precoded prior to transmission, as described in [7]. Specif- I I aP ically, the signal path values are encoded according to the following @xAa p e dX (8) P% equation: x For comparison, the fully differential system shown in Fig. 2 would y a@y C u A v kCI k k mod (4) have the following probability of error: 1To minimize power consumption, differential signals are usually driven in a p balanced fashion so that y a y . e a P X (9) 296 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL.