Section 1 The IBM 701-7094 II sequence, a family by evolution The IBM 701, 704, 709, 7090, 7040, 7044, 7094 I, and 7094 _T, console - II sequence relationship is shown in Fig. 1. The group is not I 2_Kio-Sf) a compatible series. The IBM 701 [Astrahan and Rochester, Mp!_Pc -TMine; printer; 150 line/min;] col/line J 1952; Buchholz, 1953] is a forerunner of the series; all except [72/120 card; reader; 150 card/mln the 701 are painfully compatible. The sequence is included _72/80 col/card because the 7090 is a reference or benchmark of scientific- card; punch; 100 card/mi n; All machines use 36-bit words. The 701 stores computer power. 72/80 col /card two instructions/word in the same manner as the IAS computer — K—Sfx— Ms : f#0:3; drum; t .access _ 80 ms" 4), whereas all others in the store one (Chap. sequence only |_i,rate: 1200200 u,s w - instruction /word. The 701, 704, and 709 are first-generation, K—Sfx— Ms "#0:3; magnetic tape; 1250 w/s; vacuum-tube technology; the rest are second-generation. 1400 ft; 200 w/ft; 6 char/w; -6 b/char - The IBM 7094 II description given in Chap. 41 is based directly on information in the Programming Reference Manual, Mp(electrostatlc; random; 24 us/w; 2048 w; 36 b/w) but the Appendices of that chapter give the ISP of the Pc, a Pc(2 instructions/w; M. : processor state(~3w ) 1 address/ Pio, and a K as inferred by the authors of this book. The Instruction; 36 b/w; technology: vacuum tubes: descendants: description of the Pc gives the instructions in the 704 and 7044 IBM 704, IBM 709: 1953 ~ 1956) Fig. 2. IBM 701 PMS diagram. to show an evolution. However, the major evolutionary change does not appear in Pc's ISP but in the PMS structure. 5 7 The 704 structure, like that of the 701 2), provides C(7094I) CI7094H) (Fig. only 7094 for peripheral transfers to via Pc under 3 primary memory pro- C(709) 4 709 ..C17090) grammed control with no interrupt system. As such, only one C(704) C(7040,7044)° 704 T or Ms could operate easily at a time. The 709 introduced the Pio('Data Channels) to the to transfer data 701 ,C(701) improve ability between Mp and Ms without requiring Pc intervention. Concur- 1953 1955 1957 , 1959 1961 1963 1965 8 rent of several I/O devices is carried out Yearffirst delivery) operation by multiple Pio's the lines of the II 1 along 7094 PMS structure (Fig. 1, Chap. C(1BM 701;vacuum lube; 36 b/w; 2 instruction /w; simitar to IAS/ von Neumann controlled I/O data transmission C; program ; 41, page 518). However, the utilization of the data channels (electrostatic Mp ; 30 ^s )) tends to be rather low, when the data channel is C(IBM 704; vacuum tube; 36 b/w, 1 instruction /w; program controlled particularly I/O, traps, interrupts, Mps{AC,MQ,3 Index Registers Instruction controlling very slow devices (e.g., card equipment and line Counter) Mp (core; 12 ^sl) 3 C(IBM 704 709; upward compatible; Pio controlled data transmission) printers). When operating a high-speed tape unit at 90,000 x 6 "CUBM 7090, transistor; Mp(core; 2.18 s)) 5 h C(IBM 70941; upward 7090 compatible; overlapped memory; bits/sec the utilization of the data channel is still only approxi- Mps(7Index Registers; Pio ('7909); Mp(2^s)) 6 mately 3 percent. A program interrupt method of data transfers C(IBM 7040,7044; Pio, program controlled I/O Mp(8,2 w s)) 7 C(IBM 7094 8 3t;Mp(1.4^s)) would have been sufficient. Adam's Associates Computer Characteristics Quarterly The incompatibility among the machines, especially the 7090-7040-7094, is disheartening, both from the point of view 1. IBM Fig. Relationships among 701, 704, 709, 7094 series. of a user and an engineer. The incremental hardware needed 515 516 Part 6 Computer families Section 1 The IBM 701-7094 II sequence, a family by evolution to achieve compatibility is inexpensive when the system price storage. Thus a user has to preserve this register when double- is considered. Also, the incremental changes in the ISP do little precision floating-point instructions are given. The reason for to increase the Pc performance. Compared with the 704, the this undoubtedly relates to field modifications and cost. In an extensive order code of the 7094 shows an evolution in which original design this would be inexcusable; in this case double- for marketing, emotional, or analytic reasons new instructions precision floating point is undoubtedly worth the loss of sense were added. The index registers and their instructions are a indicators. good example of this trend. The 7094 has a very general set All in all, the designers of the 704-7094 II provided increased of index-register transmission instructions; if implemented generality through evolution. They gradually ran out of patching properly, they are probably easier to provide than the original time, technology, instruction encoding space, and memory 704 instructions. addressing bits, while exceeding compatibility constraints. It In the implementation of the double-precision floating-point was indeed time to create the IBM System /360. hardware, the sense-indicator register is needed for temporary Chapter 41 The IBM 7094 I, II Introduction in one 2-microsecond acknowledged memory cycle. Thus Mp is Core 2 16384 1 The IBM 7094 I and 7094 II computers are the last of a series Mp('7302 Storage; jtis/w; w; (72, parity) b/w) for the 7094 and 1 .4 of with the 704 1, Mp( jus/w; 16384 w; (72, 1 parity) b/w) for the 7094 II. computers beginning IBM (Fig. 1, page 515). The series is an The S('7606 Multiplexor; time access to outgrowth of the IBM 701. Although the series is multiplexed) provides from of for scientific Mp any one nine P's. Only Pc can two 36-bit words designed (arithmetic) calculations, its speed and request at a time from for instruction structure allow it to be used Mp look-ahead and double-word for general-purpose computation. There uses operations. can be only one Pc in the system. Business-type processing which string data is efficiently han- dled conversion into by fixed-length fields at input and output. From about 1956 to 1966 the was the standard of family large Processors, P computers in the United States, there being approximately 20 701, 50 20 Three processors are described: Pc('7109, 7110 Central 704, 709, 50 7090, 130 7094 I, 125 7094 II, 120 7040, and Processing Data and 120 7044 computers in existence. Unit/CPU), Pio('7607 Channel), Pio('7909 Data Chan- The PMS structure is a nel). single central processor (Pc) with All P's behave similarly in that Pc instructions and Pio com- multiple input/output processors (Pio's) (for all except the 701 and 1 The Pio's mands are fetched (or from and then 704). provide for multiple transfers to primary memory requested) Mp interpreted in P. An instruction location counter in (Mp) at high information flow rates. The structure allows for P addresses the next connection to terminal instruction. A processor instruction in turn, the duplex (T) or secondary-memory (Ms) may, require control to access for data, to to (K). This provision permits the system to be used in real- processor Mp perform transfers, modify time its state, etc. the P's are applications requiring significant computation, high-data-rate Although structurally similar, organiza- transfers with other tionally the Pc is to the Pc issues systems, and high availability. However, the superior Pio('Data Channel's; was not programs to Pio's and start and Pio's. system initially designed for time sharing and multipro- stops (controls) and communication is between Pc and the Pio's. gramming use, the attempt to so use it required modification Two-way required Tasks or for Pio's are first set in [Corbato et al., 1962]. (jobs programs) up Mp by Pc. then The word is 36 bits. Pc demands that Pio execute the length There is one single-address instruc- program independently In all but the 7094 under its own control. Initialization takes when Pc sets the tion/word. the processor interprets instructions place In instruction counter of a Pio. task in an serially. the 7094 one register instruction look-ahead is used. Upon completion Pio, The Pc has index is sent to Pc from Pio. registers, the 704 being the first IBM computer interrupt request Below we first a to use them. Their number increased from three in the 704 ~ 7090 give description of the Pc. Then the Pio('7909) to seven in the as their is presented in detail and the is outlined. The reader 7094, usefulness became apparent. Pio('7607) should the compare two Pio's. The Pio('7909) is a later design than the Pio('7607). It interprets instructions for the block of data being Structure transferred and issues instructions to the KMs or KT. The earlier the instructions for the informa- A tree-structured I Pio('7607) interprets controlling simple IBM 7094 using PMS is shown in Fig. tion the 1 and a being transferred; Pc interprets and issues the instructions using conventional block diagram in Fig. 2. to KMs or KT. The 7909 is therefore able to control more closely a or Primary memory (Mp) and P-Mp switch T Ms using a single program without need for Pc intervention.