Design of Robust CMOS Circuits for Soft Error Tolerance Debopriyo Chowdhury, Mohammad Amin Arbabian Department of EECS, Univ. of California, Berkeley, CA 94720 Abstract - With the continuous downscaling of technology, take care of the problems and analyze the merits and lowering of supply voltage and increase of operating demerits. Finally, we want to design robust latches and frequency, integrated circuits become increasingly susceptible combinational blocks that have good soft-error tolerance. to single event effects (SEE) caused by high energy particles The report is organized into four sections; section II covers like alpha particles, neutrons from cosmic rays etc. A SEU the background, origin and effect of soft error on may cause a bit flip in some latch or memory element, thereby altering the state of the system, leading to a ‘soft error’. Soft nanometer circuits. Section III is a literature review with an errors in memory have traditionally been a much greater analytical flavor, while section IV outlines the proposed concern than soft errors in logic circuits. However, as process work for the rest of the semester as well as shows some technology scales below 100 nanometers, voltage levels go initial simulation results. down and noise margins reduce, soft errors in logic circuits seem to be a potential threat too. In this work, we propose to analyze the effect of various circuit parameters on soft error susceptibility of logic circuits. Also, we plan to design a robust II. SOFT ERRORS: ORIGIN AND EFFECT ON latch that has simultaneous SET and SEU tolerance. INTEGRATED CIRCUITS Index Terms - Soft Errors, SET, SEU Hardened Latch A soft error occurs when a radiation event causes enough of a charge distribution to reverse or flip the data state of a memory cell, latch, flip-flop or even a node in a I. INTRODUCTION combinational block. The error is “soft” because the circuit or the device is not permanently damaged by the radiation. The continuous down-scaling of technology over the past Soft error is also referred to as “single event effect”. If the decade has brought about tremendous boost in performance radiation is of a very high energy, more than a single bit and levels of integration of CMOS VLSI circuits. However, may be affected, creating a mutibit upset (MBU). However, drastic device shrinking, increased complexity, lowering of MBUs are only a very small fraction of the total observed power supply, and increased frequency of operation that soft error upset rate. At this time, it is very important to accompany the technological evolution to the nanometer make a distinction between “single event transients” (SET) regime have reduced dramatically the reliability of deeply and “single event upset” (SEU). When a sensitive node, scaled ICs. A significant problem is related to soft errors typically the drain of an off transistor, is in the proximity of induced by alpha particles and atmospheric neutrons [1]. the ionization track of an electrically charged particle, it There are of course many other sources of error in ICs collects a significant part of the generated charge carriers (gate-oxide breakdowns, electromigration etc) but it is (holes or electrons), resulting in a transient current pulse on reported that whilst the total failure rate of other effects this node. Depending upon the energy of the particle, the comes to 50-200 FIT (failure in 10 9 device hours), that of transient pulse may reverse the state of that node and the SER can easily exceed 50,000 FIT/chip if no mitigation error might propagate through a sensitized path till it mechanism is employed [4]. Soft error phenomenon in reaches the flip-flop. Thus, a transient generated by a memory circuits was known to exist as early as 1970 [2], combinational block remains a transient till it is captured also radiation effects on spacecraft and airplane electronics by the flip-flop. This is referred to as SET. If the transient have been known for long [3]. Memory designers have reaches the flip-flop at a time it is active, then the transient been traditionally using error correcting codes (ECC) to will be captured by the sequential element and lead to an mitigate the effects of soft errors in memory. However, in erroneous value being stored in the flip-flop. In this case, today’s deep submicron world, soft errors pose a threat to an SET has been transformed to an SEU. In addition, a combinational and sequential circuits also. Thus, soft-error particle strike may also change the state of a flip-flop when tolerant logic design has been an area of active research it is in the hold mode and directly cause a single event during the past few years; however the problem still defies upset. SEU have received a lot of attention over the last an elegant and universal solution. In this work, we aim to few years; however with the shrinking of device sizes and investigate the effect of soft errors on circuits as they are increase of clock frequency, SETs have also become a scaled into the nanometer regime. We want to investigate threat to the reliability of digital circuits. In this work, we the various methods that have been proposed till date to aim to build circuits that provide combined resilience against SET and SEU. 1 The terrestrial environment is dominated by different generations. Electrical masking has also been decreasing mechanisms that generate (either directly or as secondary because of the reduction in node capacitance and supply reaction products) energetic ions that are responsible for voltages in every generation. Furthermore, increasing clock inducing soft errors. The magnitude of the disturbance an frequencies have reduced the time window in which latches ion causes depends on the linear energy transfer (LET) of are not transparent, thereby reducing latching-window that ion (usually measured in MeV/sq-cm/mg) [4]. Alpha masking. Thus it is clear that soft errors are really particles emitted by trace uranium and thorium impurities important in today’s era of nanometer circuits. Even though in packaging materials have been shown to be one of the the soft error rate (SER) in combinational circuits is dominant causes of soft error in integrated circuits. The currently smaller than that of sequential and memory second significant source of SER is related to cosmic rays. elements, it is expected to rise 9 orders of magnitude Primary cosmic rays react with the earth’s atmosphere to between 1992 to 2011, when it will equal the SER of produce complex cascades of secondary and tertiary unprotected memory elements [6]. particles. At terrestrial altitudes, 1% of the primary flux reaches the sea-level, where the flux is composed of protons, neutrons, pions etc [5]. Neutrons are one of the higher flux components, and since neutrons have higher LETs, they are the most likely cosmic radiation to cause upsets in devices at terrestrial altitudes. Since neutrons themselves do not generate ionization in silicon, the neutron flux alone does not define the cosmic ray component of SER. Neutrons interact with chip materials elastically and inelastically, producing ions that cause soft errors. The effect of a particle striking a node in a circuit can be modeled as a narrow current pulse of a given magnitude and duration being injected into a node. For example, a transient pulse caused by an alpha-particle can be modeled as a double exponential injection current given by [19], I (t) = I ( e -t/T1 - e -t/T2 ), where I is the maximum current, inj o o T1 is the collection time constant for a junction and T2 is Figure 1: Comparison of SRAM SER with that of logic [4] the ion track establishment time constant. There is a Qcritical for every node, which is the minimum amount of charge necessary to flip the state of the node. With the continuous downscaling of technology, the III. SOFT ERROR MITIGATION TECHNIQUES capacitance values are decreasing. Hence, for a given amount of charge transferred by an energized particle, the Research in the field of soft error has various directions: voltage change caused at a node is much greater (Q= CV). • Studying the origin of soft errors from a physics Hence, nanometer circuits are getting more susceptible to standpoint and model their exact effect on such transient errors. A simulation result is presented in semiconductor devices [4] [7] [8] Section IV to demonstrate this trend. As noted earlier, a • Development of CAD tools for soft error rate transient pulse generated at a node of a combinational analysis in integrated circuits like SERA [9] , circuit can cause error if it propagates and gets captured by ASERTA [10] , SERTOPT [10] a flip-flop. There are three mechanisms in combinational • logic circuits which mask the glitches generated by particle Introducing circuit techniques and new topologies strikes [6]: to combat soft-errors in nanometer circuits In this project, our focus is in the third direction and hence • Because of logical masking , a glitch might not this section deals with circuit techniques to make circuits propagate to a latch because of a gate on the path more robust and reliable. not being sensitized to facilitate such glitch The simplest way to take care of soft errors in logic circuits propagation, e.g. one of the inputs of a nand gate is Triple-Modular Redundancy (TMR). It’s the simplest being at zero. error masking scheme that uses three functionally • Because of electrical masking, a generated glitch equivalent copies of the logic circuit and a 2-out-of-3 might get attenuated because of the delays of the majority voter. Errors are masked and hence tolerated. gates on the path to the output Figure 2 shows the structure of a circuit that has error • Because of latching-window masking, a glitch that masking based on TMR.