DLD 2017ASSIGNMENT4 1) Implement the circuits with PLA having three inputs, four product terms, and two outputs. F1(A,B,C)=∑(0,1,2,4); F2(A,B,C)=∑(0,5,6,7); potharajuvidyasagarwors.com VBIT DLD 2017ASSIGNMENT4 2) Design and explain a 32x8 ROM. A 32 x 8 ROM consists of 32 words of 8 bits each. The five input lines are decodedby into 32 distinct outputs (memory addresses) using a 25 x 8 decoder. Each ORgate has 32 input connections à 32 x 8 ROM has internal connections 32 x 8.In general, a 2k x n ROM will have k x 2k decoder and n OR gates with 2k x ninternal connections. 3) The following is a truth table of a three‐input, four‐output combinational circuit: Inputs Outputs x y z A B C D 0 0 0 0 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 0 0 1 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 1 1 1 0 1 1 1 Tabulate the PAL programming table for the circuit, and mark the fuse map in a PAL diagram similar to the one shown in Figure below. C =A+XYZ D=Z+X’Y potharajuvidyasagarwors.com VBIT DLD 2017ASSIGNMENT4 AND Inputs Product Term x y z A Outputs 1 - 1 0 - 2 1 - 0 - A = yz′ + xz′ + x′y′z 3 0 0 1 - 4 0 0 - - B = x′y′ + xy + yz 5 1 1 - - 6 - 1 1 - 7 - - - 1 C = A + xyz 8 1 1 1 - 9 - - - - 10 - - 1 - 11 0 1 - - D = z + x′y 12 - - - - potharajuvidyasagarwors.com VBIT DLD 2017ASSIGNMENT4 4) Specify the size of a ROM (number of words and number of bits per word) that will accommodate the truth table for the following combinational circuit components: a. a binary multiplier that multiplies two 4-bit binary words, b. a 4-bit adder-subtractor, c. a quadruple two-to-one-line multiplexer with common select and enable inputs, d. a BCD-to-seven-segment decoder with an enable input. a. a binary multiplier that multiplies two 4-bit binary words, A3A2A1A0 * B3B2B1B0 = S7S6S5S4S3S2S1S0 8 inputs and 8 outputs, 256 X 8 ROM, 256 words, 8 bits each word b. a 4-bit adder-subtractor, A + B = Sum 256 X 5 ROM A – B = Difference 256 X 5 ROM Total 512 X 5 ROM c. a quadruple two-to-one-line multiplexer with common select and enable inputs, and each two-to-one-line multiplexer (with select and enable inputs) requires 4 input lines and 1 output line quadruple two-to-one-line multiplexer (with common select and enable inputs) requires 10 (4 * 4 – 2 * 3) input lines and 4 output lines 1024 X 4 ROM, 1024 words, each word 4 bits d. a BCD-to-seven-segment decoder with an enable input. 5 inputs and 7 outputs, 32 X 7 ROM DRAW THE LOGIC DIAGRAMS FOR ALL…… 5) Explain about MICRO-OPERATIONS; Arithmetic Micro-operations and Logic Micro- operations? (Write answer from my notes) potharajuvidyasagarwors.com VBIT .