PCI Local Bus Specification Production Version Revision 2.1 June 1, 1995 Revision 2.1 REVISION REVISION HISTORY DATE 1.0 Original issue 6/22/92 2.0 Incorporated connector and expansion board specification 4/30/93 2.1 Incorporated clarifications and added 66 MHz chapter 6/1/95 The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein. Contact the PCI Special Interest Group office to obtain the latest revision of the specification. Questions regarding the PCI specification or membership in the PCI Special Interest Group may be forwarded to: PCI Special Interest Group P.O. Box 14070 Portland, OR 97214 (800)433-5177 (U.S.) (503)797-4207 (International) (503)234-6762 (FAX) FireWire is a trademark of Apple Computer, Inc. Token Ring and VGA are trademarks and PS/2, IBM, Micro Channel, OS/2, and PC AT are registered trademarks of IBM Corporation. Intel386, Intel486, and i486 are trademarks and Pentium is a registered trademark of Intel Corporation. Windows is a trademark and MS-DOS and Microsoft are registered trademarks of Microsoft Corporation. Tristate is a registered trademark of National Semiconductor. NuBus is a trademark of Texas Instruments. Ethernet is a registered trademark of Xerox Corporation. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Copyright © 1992, 1993, 1995 PCI Special Interest Group ii Revision 2.1 Contents Chapter 1 Introduction 1.1. Specification Contents........................................................................................................1 1.2. Motivation .........................................................................................................................1 1.3. PCI Local Bus Applications ...............................................................................................2 1.4. PCI Local Bus Overview....................................................................................................3 1.5. PCI Local Bus Features and Benefits..................................................................................4 1.6. Administration ...................................................................................................................6 Chapter 2 Signal Definition 2.1. Signal Type Definition .......................................................................................................8 2.2. Pin Functional Groups........................................................................................................8 2.2.1. System Pins ........................................................................................................8 2.2.2. Address and Data Pins ........................................................................................9 2.2.3. Interface Control Pins ....................................................................................... 10 2.2.4. Arbitration Pins (Bus Masters Only) ................................................................. 11 2.2.5. Error Reporting Pins ......................................................................................... 12 2.2.6. Interrupt Pins (Optional) ................................................................................... 13 2.2.7. Cache Support Pins (Optional) .......................................................................... 14 2.2.8. Additional Signals ............................................................................................ 15 2.2.9. 64-Bit Bus Extension Pins (Optional) ............................................................... 16 2.2.10. JTAG/Boundary Scan Pins (Optional)............................................................. 17 2.3. Sideband Signals .............................................................................................................. 18 2.4. Central Resource Functions.............................................................................................. 19 iii Revision 2.1 Chapter 3 Bus Operation 3.1. Bus Commands ................................................................................................................21 3.1.1. Command Definition.........................................................................................21 3.1.2. Command Usage Rules .....................................................................................23 3.2. PCI Protocol Fundamentals ..............................................................................................25 3.2.1. Basic Transfer Control ......................................................................................25 3.2.2. Addressing ........................................................................................................26 3.2.3. Byte Alignment .................................................................................................29 3.2.4. Bus Driving and Turnaround .............................................................................30 3.2.5. Transaction Ordering.........................................................................................30 3.2.6. Combining, Merging, and Collapsing ................................................................33 3.3. Bus Transactions ..............................................................................................................35 3.3.1. Read Transaction...............................................................................................36 3.3.2. Write Transaction..............................................................................................37 3.3.3. Transaction Termination....................................................................................38 3.3.3.1. Master Initiated Termination ..............................................................38 3.3.3.2. Target Initiated Termination ..............................................................40 3.3.3.2.1. Target Termination Signaling Rules ...................................42 3.3.3.2.2. Requirements on a Master Because of Target Termination ......................................................................48 3.3.3.3. Delayed Transactions..........................................................................49 3.3.3.3.1. Basic Operation of a Delayed Transaction ..........................50 3.3.3.3.2. Information Required to Complete a Delayed Transaction .......................................................................51 3.3.3.3.3. Discarding a Delayed Transaction.......................................51 3.3.3.3.4. Memory Writes and Delayed Transactions..........................52 3.3.3.3.5. Delayed Transactions and LOCK#......................................52 3.3.3.3.6. Supporting Multiple Delayed Transactions .........................53 3.4. Arbitration ........................................................................................................................55 3.4.1. Arbitration Signaling Protocol ...........................................................................57 3.4.2. Fast Back-to-Back Transactions ........................................................................59 3.4.3. Arbitration Parking............................................................................................61 iv Revision 2.1 3.5. Latency ............................................................................................................................ 62 3.5.1. Target Latency.................................................................................................. 62 3.5.1.1. Target Initial Latency ........................................................................ 62 3.5.1.2. Target Subsequent Latency................................................................ 64 3.5.2. Master Data Latency ......................................................................................... 64 3.5.3. Arbitration Latency........................................................................................... 65 3.5.3.1. Bandwidth and Latency Considerations ............................................. 66 3.5.3.2. Determining Arbitration Latency ....................................................... 68 3.5.3.3. Determining Buffer Requirements ..................................................... 72 3.6. Exclusive Access.............................................................................................................. 73 3.6.1. Starting an Exclusive Access ............................................................................ 76 3.6.2. Continuing an Exclusive Access ....................................................................... 77 3.6.3. Accessing a Locked Agent................................................................................ 78 3.6.4. Completing an Exclusive Access ...................................................................... 79 3.6.5. Supporting LOCK# and Write-back Cache Coherency ...................................... 79 3.6.6. Complete Bus Lock .......................................................................................... 80 3.7. Other Bus Operations ....................................................................................................... 80 3.7.1. Device Selection ............................................................................................... 80