Intel® Quartus® Prime Pro Edition User Guide Debug Tools Updated for Intel® Quartus® Prime Design Suite: 21.2 Subscribe UG-20139 | 2021.06.21 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. System Debugging Tools Overview................................................................................. 6 1.1. System Debugging Tools Portfolio............................................................................ 6 1.1.1. System Debugging Tools Comparison........................................................... 6 1.1.2. Suggested Tools for Common Debugging Requirements.................................. 7 1.1.3. Debugging Ecosystem................................................................................ 8 1.2. Tools for Monitoring RTL Nodes................................................................................9 1.2.1. Resource Usage.........................................................................................9 1.2.2. Pin Usage............................................................................................... 11 1.2.3. Usability Enhancements............................................................................ 11 1.3. Stimulus-Capable Tools.........................................................................................12 1.3.1. In-System Sources and Probes.................................................................. 12 1.3.2. In-System Memory Content Editor..............................................................13 1.3.3. System Console.......................................................................................13 1.4. Virtual JTAG Interface Intel FPGA IP....................................................................... 14 1.5. System-Level Debug Fabric................................................................................... 14 1.6. SLD JTAG Bridge..................................................................................................14 1.6.1. SLD JTAG Bridge Index............................................................................. 15 1.6.2. Instantiating the SLD JTAG Bridge Agent.....................................................17 1.6.3. Instantiating the SLD JTAG Bridge Host.......................................................18 1.7. Partial Reconfiguration Design Debugging................................................................19 1.7.1. Debug Fabric for Partial Reconfiguration Designs.......................................... 19 1.8. System Debugging Tools Overview Revision History.................................................. 20 2. Design Debugging with the Signal Tap Logic Analyzer.................................................. 21 2.1. Signal Tap Logic Analyzer Introduction....................................................................21 2.1.1. Signal Tap Hardware and Software Requirements......................................... 23 2.2. Signal Tap Debugging Flow....................................................................................24 2.3. Step 1: Add the Signal Tap Logic Analyzer to the Project........................................... 25 2.3.1. Creating a Signal Tap Instance with the Signal Tap GUI................................. 25 2.3.2. Creating a Signal Tap Instance by HDL Instantiation..................................... 26 2.4. Step 2: Configure the Signal Tap Logic Analyzer.......................................................30 2.4.1. Specifying the Clock, Sample Depth, and RAM Type...................................... 31 2.4.2. Specifying the Buffer Acquisition Mode........................................................32 2.4.3. Adding Signals to the Signal Tap Logic Analyzer........................................... 34 2.4.4. Defining Trigger Conditions........................................................................37 2.4.5. Specifying Pipeline Settings.......................................................................60 2.4.6. Filtering Relevant Samples........................................................................ 61 2.5. Step 3: Compile the Design and Signal Tap Instances............................................... 68 2.5.1. Preserving Signals for Monitoring............................................................... 68 2.5.2. Timing Preservation................................................................................. 68 2.5.3. Prevent Changes Requiring Recompilation................................................... 69 2.5.4. Performance and Resource Considerations...................................................69 2.6. Step 4: Program the Target Hardware.....................................................................70 2.6.1. Ensure Compatibility Between .stp and .sof Files.......................................... 71 2.7. Step 5: Run the Signal Tap Logic Analyzer...............................................................71 2.7.1. Runtime Reconfigurable Options.................................................................72 2.7.2. Signal Tap Status Messages.......................................................................74 Intel Quartus Prime Pro Edition User Guide: Debug Tools Send Feedback 2 Contents 2.8. Step 6: Analyze Signal Tap Captured Data...............................................................75 2.8.1. Viewing Capture Data Using Segmented Buffers...........................................75 2.8.2. Viewing Data with Different Acquisition Modes............................................. 77 2.8.3. Creating Mnemonics for Bit Patterns........................................................... 78 2.8.4. Locating a Node in the Design................................................................... 79 2.8.5. Saving Captured Signal Tap Data............................................................... 79 2.8.6. Exporting Captured Signal Tap Data............................................................80 2.8.7. Creating a Signal Tap List File.................................................................... 80 2.9. Other Signal Tap Debugging Flows......................................................................... 81 2.9.1. Managing Multiple Signal Tap Configurations................................................ 81 2.9.2. Debugging Partial Reconfiguration Designs with Signal Tap............................ 83 2.9.3. Debugging Block-Based Designs with Signal Tap...........................................85 2.9.4. Debugging Devices that use Configuration Bitstream Security........................ 91 2.9.5. Signal Tap Data Capture with the MATLAB MEX Function................................92 2.10. Signal Tap Logic Analyzer Design Examples........................................................... 93 2.11. Custom Triggering Flow Examples........................................................................ 94 2.11.1. Trigger Example 1: Custom Trigger Position............................................... 94 2.11.2. Trigger Example 2: Trigger When triggercond1 Occurs Ten Times between triggercond2 and triggercond3...................................................... 95 2.12. Signal Tap File Templates.................................................................................... 95 2.13. Running the Stand-Alone Version of Signal Tap.......................................................98 2.14. Signal Tap Scripting Support................................................................................98 2.14.1. Signal Tap Command-Line Options............................................................98 2.14.2. Data Capture from the Command Line...................................................... 99 2.15. Signal Tap File Version Compatibility..................................................................... 99 2.16. Design Debugging with the Signal Tap Logic Analyzer Revision History.....................100 3. Quick Design Verification with Signal Probe............................................................... 104 3.1. Debug Flow with Signal Probe and Rapid Recompile................................................ 104 3.1.1. Reserve Signal Probe Pins....................................................................... 104 3.1.2. Compile the Design................................................................................ 105 3.1.3. Assign Nodes to Signal Probe Pins............................................................ 105 3.1.4. Recompile the Design............................................................................. 105 3.1.5. Check Connection Table in Fitter Report.....................................................106 3.2. Quick Design Verification with Signal Probe Revision History.................................... 107 4. In-System Debugging Using External Logic Analyzers................................................ 108 4.1. About the Intel Quartus Prime Logic Analyzer Interface........................................... 108 4.2. Choosing a Logic Analyzer................................................................................... 108 4.2.1. Required Components.............................................................................109 4.3. Flow for Using the LAI.........................................................................................110 4.3.1. Defining Parameters for the Logic Analyzer Interface...................................111 4.3.2. Mapping the LAI File Pins to Available I/O Pins........................................... 111 4.3.3. Mapping Internal Signals to the