The Defi nitive Guide to the ARM Cortex-M3 This page intentionally left blank The Defi nitive Guide to the ARM Cortex-M3 Joseph Yiu AMSTERDAM • BOSTON • HEIDELBERG • LONDON • NEW YORK OXFORD • PARIS • SAN DIEGO • SAN FRANCISCO SINGAPORE • SYDNEY • TOKYO Newnes is an imprint of Elsevier Prelims-H8534.indd iii 7/19/07 1:38:43 PM Newnes is an imprint of Elsevier 30 Corporate Drive, Suite 400, Burlington, MA 01803, USA Linacre House, Jordan Hill, Oxford OX2 8DP, UK Copyright © 2007, Elsevier Inc. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of the publisher. Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone: (ϩ44) 1865 843830, fax: (ϩ44) 1865 853333, E-mail: permissions@elsevier .com. You may also complete your request online via the Elsevier homepage (http://elsevier.com), by selecting “Support & Contact” then “Copyright and Permission” and then “Obtaining Permissions.” Recognizing the importance of preserving what has been written, Elsevier prints its books on acid-free paper whenever possible. Library of Congress Cataloging-in-Publication Data (Application submitted.) British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library. ISBN: 978-0-7506-8534-4 For information on all Newnes publications visit our Web site at www.books.elsevier.com 08 09 10 11 12 13 10 9 8 7 6 5 4 3 2 1 Typeset by Charon Tec Ltd (A Macmillan Company), Chennai, India www.charontec.com Printed in The United States of America Prelims-H8534.indd iv 7/19/07 1:38:44 PM Table of Contents Foreword ..........................................................................................................xiii Preface ..............................................................................................................xiv Acknowledgments ..............................................................................................xv Terms and Abbreviations ...................................................................................xvi Conventions .................................................................................................... xviii References .........................................................................................................xix Chapter 1 – Introduction ......................................................................................1 What Is the ARM Cortex-M3 Processor? ............................................................................1 Background of ARM and ARM Architecture ......................................................................3 A Brief History ..............................................................................................................3 Architecture Versions .....................................................................................................4 Processor Naming ..........................................................................................................6 Instruction Set Development ................................................................................................8 The Thumb-2 Instruction Set Architecture (ISA) ................................................................9 Cortex-M3 Processor Applications ....................................................................................10 Organization of This Book .................................................................................................11 Further Readings ................................................................................................................11 Chapter 2 – Overview of the Cortex-M3 .............................................................. 13 Fundamentals ......................................................................................................................13 Registers .............................................................................................................................14 R0 to R12: General-Purpose Registers ........................................................................14 R13: Stack Pointers ......................................................................................................14 R14: The Link Register ................................................................................................15 R15: The Program Counter ..........................................................................................15 Special Registers ..........................................................................................................15 Operation Modes ................................................................................................................16 The Built-In Nested Vectored Interrupt Controller ............................................................17 Nested Interrupt Support ..............................................................................................18 Vectored Interrupt Support ...........................................................................................18 Dynamic Priority Changes Support .............................................................................18 Reduction of Interrupt Latency ....................................................................................18 Interrupt Masking ........................................................................................................18 v Prelims-H8534.indd v 7/19/07 1:38:45 PM Table of Contents The Memory Map ...............................................................................................................19 The Bus Interface ...............................................................................................................20 The Memory Protection Unit .............................................................................................20 The Instruction Set .............................................................................................................20 Interrupts and Exceptions ...................................................................................................22 Debugging Support .............................................................................................................24 Characteristics Summary ....................................................................................................25 High Performance ........................................................................................................25 Advanced Interrupt-Handling Features ........................................................................25 Low Power Consumption.............................................................................................26 System Features ...........................................................................................................26 Debug Supports ............................................................................................................26 Chapter 3 – Cortex-M3 Basics ............................................................................29 Registers .............................................................................................................................29 General-Purpose Registers R0–R7 ..............................................................................29 General-Purpose Registers R8–R12 ............................................................................29 Stack Pointer R13 ........................................................................................................30 Link Register R14 ........................................................................................................32 Program Counter R15 ..................................................................................................33 Special Registers ................................................................................................................33 Program Status Registers (PSRs) .................................................................................33 PRIMASK, FAULTMASK, and BASEPRI Registers .................................................35 The Control Register ....................................................................................................36 Operation Mode ..................................................................................................................37 Exceptions and Interrupts ...................................................................................................39 Vector Tables ......................................................................................................................40 Stack Memory Operations ..................................................................................................41 Basic Operations of the Stack ......................................................................................41 Cortex-M3 Stack Implementation................................................................................42 The Two-Stack Model in the Cortex-M3 .....................................................................43 Reset Sequence ...................................................................................................................44 Chapter 4 – Instruction Sets ..............................................................................