UltraFast Design Methodology Guide for the Vivado Design Suite UG949 (v2017.1) May 26, 2017 Revision History The following table shows the revision history for this document. Date Version Revision 05/26/2017 2017.1 Updated content based on the new Vivado IDE look and feel throughout. In Chapter 3, Design Creation, added details on the ASYNC_REG attribute in Use Register Replication, added Decomposing Deeper Memory Configurations for Balanced Power and Performance, added table and updated examples in Using the CLOCK_DEDICATED_ROUTE Constraint, added SelectIO Clocking, added note about DCP files in Planning IP Requirements, and updated example in Report Timing from or to the Port. In Chapter 4, Implementation, replaced Bottom-Up Synthesis Flow with Block-Level Synthesis Strategy and updated Using Incremental Compile Flows. In Chapter 5, Design Closure, updated attribute values in Verifying That No Clocks Are Missing, added details on the congestion tables in Report Design Analysis Congestion Report, added Improving the Netlist with Block-Level Synthesis Strategies, updated Reducing Control Sets, added information on -merge_equivalent_drivers and -fanout_opt options in Use Register Replication, added -no_bufg_opt option in Promote High Fanout Nets to Global Routing, added information on router directives in Use Alternate Placer and Router Directives, added information on the MUXF_REMAP property in Disable LUT Combining and MUXF Inference, updated Use Block-Level Synthesis Strategies, added information on automatic optimization in Limit High-Fanout Nets in Congested Areas, and updated Using Incremental Compile. In Appendix A, Additional Resources and Legal Notices, removed references to Vivado Design Suite QuickTake Video: Customizing and Instantiating IP and Vivado Design Suite QuickTake Video: Designing with Vivado IP Integrator and added reference to UltraFast Design Methodology Training Course. UltraFast Design Methodology GuideSend Feedback 2 UG949 (v2017.1) May 26, 2017 www.xilinx.com Table of Contents Chapter 1: Introduction About the UltraFast Design Methodology . 5 Understanding UltraFast Design Methodology Concepts . 9 Using the Vivado Design Suite . 12 Accessing Additional Documentation and Training. 13 Chapter 2: Board and Device Planning Overview of Board and Device Planning . 14 PCB Layout Recommendations . 14 Clock Resource Planning and Assignment . 17 I/O Planning Design Flows. 18 Designing with SSI Devices . 24 FPGA Power Aspects and System Dependencies. 30 Configuration . 33 Chapter 3: Design Creation Overview of Design Creation. 34 Defining a Good Design Hierarchy . 35 RTL Coding Guidelines . 38 Clocking Guidelines . 75 Clock Domain Crossing . 128 Working With Intellectual Property (IP). 132 Working with Constraints . 136 Chapter 4: Implementation Overview of Synthesis and Implementation . 177 Running Synthesis . 177 Moving Past Synthesis. 180 Implementing the Design . 184 Chapter 5: Design Closure Overview of Design Closure . 190 Timing Closure . 190 UltraFast Design Methodology GuideSend Feedback 3 UG949 (v2017.1) May 26, 2017 www.xilinx.com Analyzing and Resolving Timing Violations . 208 Applying Common Timing Closure Techniques . 233 Power Analysis and Optimization. 259 Configuration and Debug . 262 Appendix A: Additional Resources and Legal Notices Xilinx Resources . 272 Solution Centers. 272 Documentation Navigator and Design Hubs . 272 References . 273 Training Resources. 275 Please Read: Important Legal Notices . 276 UltraFast Design Methodology GuideSend Feedback 4 UG949 (v2017.1) May 26, 2017 www.xilinx.com Chapter 1 Introduction About the UltraFast Design Methodology The Xilinx® UltraFast™ design methodology is a set of best practices intended to help streamline the design process for today’s All Programmable devices. The size and complexity of these designs require specific steps and design tasks to ensure success at each stage of the design. Following these steps and adhering to the best practices will help you achieve your desired design goals as quickly and efficiently as possible. Xilinx provides the following resources to help you take advantage of the UltraFast design methodology: • This guide, which describes the various design tasks, analysis and reporting features, and best practices for design creation and closure. • UltraFast Design Methodology checklist, which is available in the Xilinx Documentation Navigator and as a standalone spreadsheet. You can use this checklist to identify common mistakes and decision points throughout the design process. • Methodology-related design rule checks (DRCs) for each design stage, which are available using the report_methodology Tcl command in the Vivado® Design Suite. • UltraFast Design Methodology System-Level Design Flow diagram representing the entire Vivado Design Suite design flow, which is available in the Xilinx Documentation Navigator. You can click a design step in the diagram to open related documentation, collateral, and FAQs to hep get you started. UltraFast Design Methodology GuideSend Feedback 5 UG949 (v2017.1) May 26, 2017 www.xilinx.com Chapter 1: Introduction Using This Guide This guide provides a set of best practices that maximize productivity for both system integration and design implementation. It includes high-level information, design guidelines, and design decision trade-offs for the following topics: • Chapter 2, Board and Device Planning: Covers decisions and design tasks that Xilinx recommends accomplishing prior to design creation. These include I/O and clock planning, PCB layout considerations, device capacity and throughput assessment, alternate device definition, power estimation, and debugging. • Chapter 3, Design Creation: Covers the best practices for RTL definition, IP configuration and management, and constraints assignment. • Chapter 4, Implementation: Covers the options available and best practices for synthesizing and implementing the design. • Chapter 5, Design Closure: Covers the various design analysis and implementation techniques used to close timing on the design or to reduce power consumption. It also includes considerations for adding debug logic to the design for hardware verification purposes. This guide includes references to other documents such as the Vivado Design Suite User Guides, Vivado Design Suite Tutorials, and Quick-Take Video Tutorials. This guide is not a replacement for those documents. Xilinx still recommends referring to those documents for detailed information, including descriptions of tool use and design methodology. For a listing of reference documents, see Appendix A, Additional Resources and Legal Notices. Note: This information is designed for use with the Vivado Design Suite, but you can use most of the conceptual information with the ISE® Design Suite as well. Using the UltraFast Design Methodology Checklist To take full advantage of the UltraFast design methodology, use this guide with the UltraFast Design Methodology Checklist. The checklist is available from the Xilinx Documentation Navigator or as a standalone spreadsheet (XTP301). UltraFast Design Methodology GuideSend Feedback 6 UG949 (v2017.1) May 26, 2017 www.xilinx.com Chapter 1: Introduction The questions in the UltraFast Design Methodology Checklist highlight typical areas in which design decisions are likely to have downstream impact and draw attention to issues that are often overlooked or ignored. Each tab in the checklist: • Targets a specific role within a typical design team. • Includes common questions and recommended actions to take during each design flow step, including project planning, board and device planning, IP and submodule design, and top-level design closure. • Includes a Documentation and Training section that lists resources related to the design flow step. • Provides links to content in this guide or other Xilinx documentation, which offer guidance on addressing the design concerns raised by the questions. VIDEO: For a demonstration of the checklist, see the Vivado Design Suite QuickTake Video: Introducing the UltraFast Design Methodology Checklist. Using the UltraFast Design Methodology DRCs The Vivado Design Suite contains a set of methodology-related DRCs you can run using the report_methodology Tcl command. This command has rules for each of the following design stages: • Before synthesis in the elaborated RTL design to validate RTL constructs • After synthesis to validate the netlist and constraints • After implementation to validate constraints and timing related concerns. RECOMMENDED: For maximum effect, run the methodology DRCs at each design stage and address any issues prior to moving to the next stage. For more information on the design methodology DRCs, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906) [Ref 21], and see the report_methodology Tcl command in the Vivado Design Suite Tcl Command Reference Guide (UG835) [Ref 13]. UltraFast Design Methodology GuideSend Feedback 7 UG949 (v2017.1) May 26, 2017 www.xilinx.com Chapter 1: Introduction Using the UltraFast Design Methodology System-Level Design Flow Diagram The following figure shows the various design steps and features included in the Vivado Design Suite. From the Xilinx Documentation Navigator, you can access an interactive version of this graphic in which you can click each step for links to related resources. X-Ref Target - Figure 1-1 System Design Entry Software Development C-Based Design DSP Design with with High-Level Synthesis System Generator Configuring Xilinx