Intel® Quartus® Prime Pro Edition User Guide Design Optimization Updated for Intel® Quartus® Prime Design Suite: 21.2 Subscribe UG-20133 | 2021.06.23 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. Design Optimization Overview........................................................................................ 6 1.1. Device Considerations............................................................................................ 6 1.1.1. Device Migration Considerations.................................................................. 6 1.2. Required Settings for Initial Compilation................................................................... 7 1.2.1. Initial I/O Assignment Guidelines................................................................. 7 1.2.2. Initial Timing Constraint Guidelines.............................................................. 7 1.3. Optimization Trade-Offs and Limitations....................................................................8 1.3.1. Area Reduction Trade-Offs...........................................................................8 1.3.2. Critical Path Delay Reduction Trade-Offs........................................................8 1.3.3. Power Consumption Reduction Trade-Offs..................................................... 9 1.3.4. Compilation Time Trade-Offs....................................................................... 9 1.4. Design Visualization and Optimization Tools...............................................................9 1.4.1. Design Visualization Tools........................................................................... 9 1.4.2. Design Optimization Tools......................................................................... 10 1.5. Design Optimization Overview Revision History........................................................ 11 2. Optimizing the Design Netlist....................................................................................... 13 2.1. When to Use the Netlist Viewers: Analyzing Design Problems ....................................13 2.2. Intel Quartus Prime Design Flow with the Netlist Viewers.......................................... 14 2.3. RTL Viewer Overview............................................................................................15 2.3.1. Maximizing Readability in RTL Viewer..........................................................16 2.3.2. Running the RTL Viewer............................................................................ 16 2.4. Technology Map Viewer Overview...........................................................................16 2.5. Netlist Viewer User Interface................................................................................. 17 2.5.1. Netlist Navigator Pane.............................................................................. 20 2.5.2. Properties Pane....................................................................................... 20 2.5.3. Netlist Viewers Find Pane.......................................................................... 22 2.6. Schematic View................................................................................................... 22 2.6.1. Display Schematics in Multiple Tabbed View.................................................22 2.6.2. Schematic Symbols.................................................................................. 23 2.6.3. Select Items in the Schematic View............................................................ 27 2.6.4. Shortcut Menu Commands in the Schematic View.........................................27 2.6.5. Filtering in the Schematic View.................................................................. 28 2.6.6. View Contents of Nodes in the Schematic View............................................ 28 2.6.7. Moving Nodes in the Schematic View.......................................................... 30 2.6.8. View LUT Representations in the Technology Map Viewer............................... 31 2.6.9. Zoom Controls.........................................................................................31 2.6.10. Navigating with the Bird's Eye View.......................................................... 32 2.6.11. Partition the Schematic into Pages............................................................32 2.6.12. Follow Nets Across Schematic Pages......................................................... 33 2.6.13. Maintaining Selection in the Resource Property Viewer................................ 33 2.7. Cross-Probing to a Source Design File and Other Intel Quartus Prime Windows............ 34 2.8. Cross-Probing to the Netlist Viewers from Other Intel Quartus Prime Windows............. 35 2.9. Viewing a Timing Path.......................................................................................... 36 2.10. Optimizing the Design Netlist Revision History........................................................36 3. Netlist Optimizations and Physical Synthesis................................................................ 38 3.1. Physical Synthesis Optimizations............................................................................38 Intel Quartus Prime Pro Edition User Guide: Design Optimization Send Feedback 2 Contents 3.1.1. Enabling Physical Synthesis Optimization.................................................... 39 3.1.2. Physical Synthesis Options........................................................................ 39 3.2. Applying Netlist Optimizations............................................................................... 39 3.2.1. WYSIWYG Primitive Resynthesis.................................................................40 3.3. Scripting Support.................................................................................................41 3.3.1. Synthesis Netlist Optimizations.................................................................. 41 3.3.2. Physical Synthesis Optimizations................................................................42 3.4. Netlist Optimizations and Physical Synthesis Revision History.....................................42 4. Area Optimization......................................................................................................... 44 4.1. Resource Utilization Information............................................................................ 44 4.1.1. Flow Summary Report.............................................................................. 44 4.1.2. Fitter Reports.......................................................................................... 45 4.1.3. Analysis and Synthesis Reports..................................................................45 4.1.4. Compilation Messages.............................................................................. 45 4.2. Optimizing Resource Utilization..............................................................................46 4.2.1. Resource Utilization Issues Overview.......................................................... 46 4.2.2. I/O Pin Utilization or Placement..................................................................46 4.2.3. Logic Utilization or Placement.................................................................... 47 4.2.4. Routing.................................................................................................. 51 4.3. Scripting Support.................................................................................................53 4.3.1. Initial Compilation Settings....................................................................... 54 4.3.2. Resource Utilization Optimization Techniques............................................... 54 4.4. Area Optimization Revision History.........................................................................55 5. Timing Closure and Optimization.................................................................................. 56 5.1. Optimize Multi Corner Timing................................................................................ 56 5.2. Optimize Critical Paths..........................................................................................56 5.2.1. Viewing Critical Paths............................................................................... 57 5.3. Optimize Critical Chains........................................................................................ 57 5.3.1. Viewing Critical Chains..............................................................................57 5.4. Design Evaluation for Timing Closure......................................................................58 5.4.1. Review Messages..................................................................................... 58 5.4.2. Evaluate Fitter Netlist Optimizations........................................................... 58 5.4.3. Evaluate Optimization Results....................................................................58 5.4.4. Evaluate Resource Usage.......................................................................... 58 5.4.5. Evaluate Other Reports and Adjust Settings Accordingly................................ 62 5.4.6. Evaluate Clustering Difficulty..................................................................... 64 5.4.7. Revise and Recompile...............................................................................64 5.5. Timing Optimization............................................................................................. 64 5.5.1. Correct Design Assistant Rule