Carnegie Mellon Virtual Memory, Dynamic Memory Alloca3on, Malloc Lab 15-213: Introduc0on to Computer Systems 10th July, 2014 Vinay Venkatesh (vinayven) Shivaram Shankar (sshankar) Aditya Gupta (adityag1) 1 Carnegie Mellon Agenda ! Virtual Memory Concepts ! Address Transla3on ! Basic ! TLB ! Mul0level ! Dynamic Memory Alloca3on ! Malloc Lab 2 Carnegie Mellon Virtual Memory Concepts Memory ! We’ve been viewing Kernel virtual memory invisible to user code memory as a linear 0xC0000000 User stack (created at runme) array. %esp (stack pointer) ! But wait! If you’re running 5 processes Memory-mapped region for shared libraries with stacks at 0x40000000 0xC0000000, don’t brk their addresses Run-3me heap conflict? (created by malloc) Read/write segment ! Nope! Each process has (.data, .bss) Loaded from the executable Read-only segment its own address space. file (.init, .text, .rodata) 0x08048000 ! How??? Unused 3 Carnegie Mellon Virtual memory concepts ! We define a mappinG from the virtual address used by the process to the actual physical address of the data in memory. Image: hYp://en.wikipedia.orG/wiki/ File:Virtual_address_space_and_p hysical_address_space_relaonshi p.svG 4 Carnegie Mellon Virtual memory concepts This explains why two different processes can use the same address. It also lets them share data and protects their data from illeGal accesses. Hooray for virtual memory! 0 Address 0 Virtual Physical Address VP 1 transla>on Address Space for VP 2 PP 2 Space Process 1: ... (DRAM) N-1 (e.g., read-only PP 6 library code) 0 Virtual PP 8 Address VP 1 Space for VP 2 ... Process 2: ... N-1 M-1 5 Carnegie Mellon Virtual memory concepts ! Page table ! Lets us look up the physical address correspondinG to any virtual address. (Array of physical addresses, indexed by virtual address.) ! TLB (Translaon Lookaside Buffer) ! A special 0ny cache just for page table entries. ! Speeds up translaon. ! Mul3-level page tables ! The address space is o`en sparse. ! Use page directory to map larGe chunks of memory to a page table. ! Mark larGe unmapped reGions as non-present in page directory instead of storinG page tables full of invalid entries. 6 Carnegie Mellon VM Address Transla3on ! Virtual Address Space ! V = {0, 1, …, N–1} ! There are N possible virtual addresses. ! Virtual addresses are n bits lonG; 2n = N. ! Physical Address Space ! P = {0, 1, …, M–1} ! There are M possible physical addresses. ! Virtual addresses are m bits lonG; 2m = M. ! Memory is grouped into “pages.” ! Page size is P bytes. ! The address offset is p bytes; 2p = P. ! Since the virtual offset (VPO) and physical offset (PPO) are the same, the offset doesn’t need to be translated. 7 Carnegie Mellon VM Address Transla3on Virtual address n-1 p p-1 0 Page table base register Virtual page number (VPN) Virtual page offset (VPO) (PTBR) Page table address Page table for process Valid Physical page number (PPN) Valid bit = 0: page not in memory (page fault) m-1 p p-1 0 Physical page number (PPN) Physical page offset (PPO) Physical address 8 Carnegie Mellon VM Address Transla3on with TLB ! That’s nice and simple, but it doubles memory usage. ! One memory access to look in the page table. ! One memory access of the actual memory we’re lookinG for. ! Soluon: ! Cache the most frequently used page table entries in the TLB. ! To look up a virtual address in the TLB, split up the VPN (not the whole virtual address!) into a TLB index and a TLB tag. CPU TLB Chip 2 PTE VPN 3 1 VA PA CPU MMU 4 Cache/ Memory Data 5 9 Carnegie Mellon Example 2: Address Translaon with TLB 1 MB of virtual memory 4 KB page size 256 KB of physical memory TLB: 8 entries, 2-way set associave ! How many bits are needed to represent the virtual address space? ! How many bits are needed to represent the physical address space? ! How many bits are needed to represent the offset? ! How many bits are needed to represent VPN? ! How many bits are in the TLB index? ! How many bits are in the TLB tag? 10 Carnegie Mellon Example 2: Address Translaon with TLB 1 MB of virtual memory 4 KB page size 256 KB of physical memory TLB: 8 entries, 2-way set associave ! How many bits are needed to represent the virtual address space? 20. (1 MB = 220 bytes.) ! How many bits are needed to represent the physical address space? 18. (256 KB = 218 bytes.) ! How many bits are needed to represent the offset? 12. (4 KB = 212 bytes.) ! How many bits are needed to represent VPN? 8. (20-12.) ! How many bits are in the TLB index? 2. (4 sets = 22 set bits.) ! How many bits are in the TLB tag? 6. (8-2.) 11 Carnegie Mellon Example 2b: Address Transla3on with TLB ! Translate 0x1F213, given the contents of TLB and the first 32 entries of the page table below. 12 Carnegie Mellon Example 2b: Address Transla3on with TLB 0x1F213 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VPN VPO VPN: TLBI: TLBT: 13 Carnegie Mellon Example 2b: Address Transla3on with TLB TLBT TLBI 0x1F213 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 1 VPN VPO VPN: 0x1F TLB Miss! TLBI: 0x03 TLBT: 0x07 Step 2: look it up in the page table. ! 14 Carnegie Mellon Example 2b: Address Transla3on with TLB TLBT TLBI 0x1F213 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 1 VPN VPO VPN: 0x1F Page Table Hit TLBI: 0x03 PPN: TLBT: 0x07 Offset: Physical address: 15 Carnegie Mellon Example 2b: Address Transla3on with TLB TLBT TLBI 0x1F213 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 1 1 1 0 0 1 0 0 0 0 1 0 0 1 1 VPN VPO VPN: 0x1F Page Table Hit TLBI: 0x03 PPN: 0x15 TLBT: 0x07 Offset: 0x213 Physical address: 0x15213 16 Carnegie Mellon VM Address Transla3on In Real Life ! Page tables are oeen mul-level, with the first level called the “page directory.” ! This example uses Intel IA-32 conven3ons. ! To index into k levels, divide VPN into k parts. (diagrams in the followinG slides are from Intel System ProGrammers Guide) 17 Carnegie Mellon VM Address Transla3on In Real Life ! Page tables are oeen mul-level, with the first level called the “page directory.” ! This example uses Intel IA-32 conven3ons. ! To index into k levels, divide VPN into k parts. (diagrams in the followinG slides are from Intel System ProGrammers Guide) 18 Carnegie Mellon 19 Carnegie Mellon 20 Carnegie Mellon Malloc Lab 35 .