See all versions of this document Versal ACAP System Integration and Validation Methodology Guide UG1388 (v2021.1) July 26, 2021 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 07/26/2021 Version 2021.1 Logic Simulation Using SystemC Models Added CIPS VIP to table. NoC Emulation Added PG313 link and updated title. Chapter 3: Design Closure Updated design closure description. Timing Closure Added timing result note. Checking for Valid Constraints Added baselining design to note. Checking for Positive Timing Slacks Updated to timing score description. Checking That Your Design is Properly Constrained Added timing constraint note. Fixing Issues Flagged by report_methodology Added methodology violation note and link to methodology blog. Methodology DRCs with Impact on Timing Closure Added UG906 link. Assessing the Maximum Frequency of the Design Updated WNS description. Analyzing and Resolving Timing Violations Updated Analyzing and Resolving Timing Violations figure. Clock Skew and Uncertainty Added clock uncertainty description and related links. Timing Closure Added report_qor_suggestions note throughout subsections. Reducing Clock Delay in Versal Devices Added section. Power Closure Added power optimization capabilities description. Power Timing Slack Added section. Analyzing System Performance for Platform-Based Designs Updated title and added traditional design note. Analyzing AI Engine Performance in Simulation Added AI Engine bottleneck description. Measuring Performance with AI Engine Run Time Event APIs Updated event API code block. JTAG Status and Error Status Added POR description. Rails Voltage Status Updated Register PWR_SUPPLY_STATUS Bit-Field Details table. Debugging the NoC Added section. Debugging with SmartLynq+ Added SmartLynq+ link. Using VIO Cores Added link to PG364. Using IBERT GTY for Transceiver Link Characterization Added link to PG331. Using the ChipScoPy Python Client For Debugging Added section. Debugging the Software Added section. Performance Validation Added link to UG1076. UG1388 (v2021.1) July 26, 2021Send Feedback www.xilinx.com Versal ACAP System Integration and Validation Methodology 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Introduction.............................................................................................. 5 About the Versal ACAP Design Methodology.......................................................................... 5 Navigating Content by Design Process.................................................................................... 5 About This Guide......................................................................................................................... 6 Chapter 2: Simulation Flows.....................................................................................7 Logic Simulation.......................................................................................................................... 7 HLS Simulation.............................................................................................................................8 AI Engine Simulation...................................................................................................................9 Embedded Software Simulation................................................................................................9 Hardware Emulation................................................................................................................. 10 Chapter 3: Design Closure........................................................................................12 Timing Closure...........................................................................................................................13 Power Closure............................................................................................................................78 Chapter 4: System Performance Closure.........................................................83 Analyzing System Performance for Platform-Based Designs..............................................83 Improving Performance in the PS...........................................................................................89 Improving Performance in the PL...........................................................................................91 Improving Performance Through the NoC............................................................................97 Improving Performance in the AI Engine.............................................................................. 99 Improving Performance Through the CPM and PL PCIe......................................................99 Chapter 5: Configuration and Debug.............................................................. 105 Configuration...........................................................................................................................105 Debugging............................................................................................................................... 106 Chapter 6: Validation................................................................................................ 127 Block and IP Validation .......................................................................................................... 127 AI Engine Design Validation...................................................................................................129 UG1388 (v2021.1) July 26, 2021Send Feedback www.xilinx.com Versal ACAP System Integration and Validation Methodology 3 System Validation....................................................................................................................131 Design Debug.......................................................................................................................... 131 Appendix A: Additional Resources and Legal Notices........................... 132 Xilinx Resources.......................................................................................................................132 Solution Centers...................................................................................................................... 132 Documentation Navigator and Design Hubs...................................................................... 132 References................................................................................................................................133 Training Resources..................................................................................................................136 Please Read: Important Legal Notices................................................................................. 136 UG1388 (v2021.1) July 26, 2021Send Feedback www.xilinx.com Versal ACAP System Integration and Validation Methodology 4 Chapter 1: Introduction Chapter 1 Introduction About the Versal ACAP Design Methodology The Xilinx® Versal™ adaptive compute acceleration platform (ACAP) design methodology is a set of best practices intended to help streamline the design process for Versal devices. The size and complexity of these designs require specific steps and design tasks to ensure success at each stage of the design. Following these steps and adhering to the best practices will help you achieve your desired design goals as quickly and efficiently as possible. Navigating Content by Design Process Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal™ ACAP design process Design Hubs can be found on the Xilinx.com website. This document covers the following design processes: • System Integration and Validation: Integrating and validating the system functional performance, including timing, resource use, and power closure. For additional methodology information, see the following documents: • System and Solution Planning: Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. See the Versal ACAP Design Guide (UG1273) and Versal ACAP System and Solution Planning Methodology Guide (UG1504). • Embedded Software Development: Creating the software platform from the hardware platform and developing the application code using the embedded CPU. Also covers XRT and Graph APIs. See the Programming the PS Host Application in the AI Engine Documentation flow of the Vitis Unified Software Platform Documentation (UG1416). • AI Engine Development: Creating the AI Engine graph and kernels, library use, simulation debugging and profiling, and algorithm development. Also includes the integration of the PL and AI Engine kernels. See the Versal ACAP AI Engine Programming Environment User Guide (UG1076) and Versal ACAP AI Engine Kernel Coding Best Practices Guide (UG1079). UG1388 (v2021.1) July 26, 2021Send Feedback www.xilinx.com Versal ACAP System Integration and Validation Methodology 5 Chapter 1: Introduction • Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware platform, creating PL kernels, functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. See the Versal ACAP Hardware, IP, and Platform Development Methodology Guide (UG1387).