Phase Noise Simulation and Modeling of ADPLL by SystemVerilog Tingjun Wen Tad Kwasniewski Integrated Device Technology, Canada Department of Electronics, Carleton University Ottawa, Ontario, Canada K2K 3K2 Ottawa, Ontario, Canada K1S 5B6 [email protected] [email protected] Abstract—Event driven phase noise simulation and modeling of to worry about how event driven functions work. Adding a an ADPLL by SystemVerilog is presented in this paper. It uses the Σ∆ modulator into the simulation code will make it possible simple Stochastic Voss-McCartney algorithm to generate the pink to study the Σ∆ modulator phase noise effect. Reference [3] noise so that the 1/f phase noise effect can be easily modeled. Since the event driven simulation is extremely fast compared does this by a different mixed signal simulator SpectreVerilog to the circuit level simulation, it allows circuit designers to from Cadence. With the advance of the CMOS process, more explore different ADPLL architectures at the early stage without and more circuit components can be integrated into a single going through the time-consuming circuit level simulation. Pure chip and most SOC designs have one or more PLL blocks. SystemVerilog implementation also makes it possible to simulate From the architectural point of view, it is desirable to use as the phase noise effect of the ADPLL efficiently in a large SOC system. many as possible digital parts in the PLL design. This results in the proliferation of the ADPLL in the SOC applications. I. INTRODUCTION Due to ADPLL’s digital nature, it is very easy to incorporate It is a well known issue that the phase locked loop (PLL) the ADPLL simulation into the SOC simulation environment. simulation by Spice-like simulator is time consuming. In order It is a difficult task to effectively simulate the phase noise in to predict the noise in a circuit, Spice needs a quiescent a pure digital environment without slowing down the whole operating point which is not always the case in a PLL circuit simulation because phase noise simulation requires complex [1]. This means that it is impractical to use Spice simulator to noise generation algorithms. Reference [4] simulates the phase explore the PLL architecture due to its simulation speed and noise within the SOC environment with the pure digital VHDL sometimes it is even impossible due to its inability to simulate language. the noise in a complex system. In order to solve the speed The key component in the phase noise simulation is the problem of the Spice simulation, phase-domain simulation time domain noise generator. Once the noise in the digital technique was used. However, the phase domain simulation controlled oscillator (DCO) is generated correctly, the closed is only useful for predicting the loop dynamics and gives loop dynamics with the noise effect can be simulated. The little intuitive insight into the circuit itself especially for the most important noises in a DCO is the −20dB/dec frequency beginners. Moreover, the phase domain simulation can not be modulated thermal noise, the −10dB/dec flicker noise, and used to evaluate the phase noise performance which is the the flat white Gaussian noise. Noises generated in blocks that most important feature in a PLL system. are not part of the PLL loop can be modeled as the additive With the increased interest in the all digital phase locked white noise and they are not cumulative so they can be inferred loop (ADPLL), researchers began to simulate the ADPLL by into the DCO’s output white noise. the event driven technique. Reference [2] explores Matlab’s This paper first briefly explains a new ADPLL architecture event driven programming technique to simulate the digital that the authors are currently working on in section II. Sys- PLL at the system level. Because the Matlab simulation temVerilog is used to model this ADPLL building blocks since code uses the event driven functions, the simulation speed SystemVerilog’s direct programing interface (DPI) makes it is fast. It is easy to add the phase noise simulation in the extremely easy to call external noise generation functions Matlab code. However, it is not an easy task to integrate the written in C. The noise generation algorithms are thoroughly Matlab simulation into a system-on-a-chip (SOC) simulation described in section III. The highly respected Mersenne- environment. Reference [1] is a comprehensive tutorial paper Twister random number generator [5] is used to generate that uses the mixed signal simulator VerilogA to simulate a the white noise with uniform distribution. The white noise charge pump PLL (CPPLL). The best part of this paper is its with Gaussian distribution is then generated from this uniform jitter and phase noise simulation technique. Compared to the white noise by the Box-Muller algorithm. The 1/f noise is Matlab or other general purpose programming languages such generated by a simple Stochastic Voss-McCartney algorithm as C, the hardware description languages Verilog or VHDL [6] from the music DSP cummunity. The higher order noises are intrinsically event driven and programmers do not need are generated by integration over the previously mentioned REF UP the UP output is high; otherwise, the DN signal is high. PDF DCO When the reference clock REF and the divide down signal DN FB have the same frequency and they are phase synchronized, both UP and DN are low. Due to the AND gate delay, there is FB OUT a very short time when both UP and DN are high. Listing 1 DIV shows the PFD SystemVerilog code. The file adpll.vh contains the design parameters and noise parameters. They can be found Fig. 1. ADPLL in Listing 4 and Listing 5. UP D Q Listing 1. PFD 1 ‘include ”adpll .vh” REF 2 module pfd (fref, fdiv, up, dn, rst n ) ; Q’ 3 output up , dn ; 4 input fref, fdiv, rst n ; 5 reg up , dn ; 6 wire p f d r s t ; 7 Q’ 8 // fref faster => up FB 9 always @( posedge fref or posedge p f d r s t ) begin D Q DN 10 if (pfd rst) up <= 0 ; else up <= 1 ; 11 end Fig. 2. PDF 12 13 // fdiv faster => dn 14 always @( posedge fdiv or posedge p f d r s t ) begin lower order noise sources. The phase noise simulation results 15 if (pfd rst) dn <= 0 ; else dn <= 1 ; of the new ADPLL architecture are presented in section IV. 16 end Finally, this paper is concluded by section V with comparisons 17 and discussions of the simulation results. 18 assign p f d r s t = ˜ r s t n | ( up & dn ) ; 19 endmodule II. ADPLL ARCHITECTURE The block diagram of the ADPLL under consideration is B. Frequency divider depicted in Fig. 1. The low speed reference signal REF is fed The frequency divider in a real circuit implementation may into the phase frequency detector (PFD). The PFD compares be the dual modulus divider. However, for the behavioral this REF with the feedback signal FB from the frequency simulation purpose, we simply use a counter. Initially, the divider (DIV) and produces two signals UP and DN. The counter is reset to 0. Whenever the counter is greater than UP and DN signals are then fed to the digitally controlled or equal to the programmed divider ratio, the output is flipped oscillator DCO. Let us denote the intrinsic output period of the and the the counter is reset to 0 again. Listing 2 shows the DCO as T0 when both UP and DN are tied to ground. The frequency divider SystemVerilog code. instantaneous output period of the DCO T is then determined Listing 2. FDIV by T0 and the state value stored in the varactor array. The high 1 ‘include ”adpll .vh” speed output signal OUT with period T is divided down to 2 module fdiv (clk, M, fdiv, reset); FB with the period of T ∗ N by the frequency divider DIV 3 parameter d i v w i d t h = 8 ; where N is the divider ratio. 4 input clk , r e s e t ; Compared to most of the traditional PLL configurations, 5 input [div width −1:0] M; this ADPLL does not have an explicit low pass filter LPF. 6 output f d i v ; 7 wire f d i v ; The LPF function in this ADPLL is tightly integrated inside 8 reg q ; the DCO. The DCO frequency is controlled by an array of 9 integer i ; switched capacitors which can also be used to perform the 10 addition operations. Integrating the LPF function inside the 11 always @( negedge reset) begin DCO has the benefit of eliminating the complex adders needed 12 i = 0 ; 13 q = 0 ; by the traditional LPF module. The detailed configuration of 14 end the DCO and its operation will be described in section II-C. 15 16 always @(clk) begin A. Phase frequency detector 17 if (˜ reset) begin 18 i = i + 1 ; The phase and frequency detector used in this simulation 19 if ( i >= M) begin is the traditional 3-state PFD as depicted in Fig. 2. When the 20 q = ˜ q ; reference clock REF is ahead of the divide down signal FB, 21 i = 0 ; TABLE I Proportional Integral Oscillator PROPORTIONAL PATH TRUTH TABLE ... UP DN P[1] P[0] P-1 00 0 1 0 0 1 0 0 -1 10 1 0 1 FB Retiming registers 11 0 1 0 P[0] P[1] 2−way shift register or up/dn counter TABLE II UP INTEGRAL PATH CODING METHODS AND EXAMPLES DN Varactor Ctrl Ctrl Varactor Granu- Coding Logic Word Change larity Fig.