AN613 Using Microchip 93 Series Serial EEPROMs with Microcontroller SPI Ports to make sure it writes (polling ready/busy pin to verify Author: Keith Pazul write cycle completion) and reads properly. A Memory and ASSP Division schematic (Figure 2) is included in this application note to describe exactly how the 93LC56/66 was connected to the microcontroller. INTRODUCTION THEORY OF OPERATION Systems requiring embedded control are becoming more and more sophisticated, with microcontrollers To use an SPI port to communicate with Microchip’s 93 required to control these systems increasing in series Serial EEPROMs, the bytes to be output to the complexity. Many microcontrollers today are being 93XXXX must be aligned such that the LSB of the designed with built-in serial communication capability address is the 8th bit (LSB) of a byte to be output. From to be able to easily access other features that are not there, the bits should fill the byte from right to left built in to the microcontroller itself. Devices like consecutively. If more than 8 bits are required, then two EEPROMs, A/Ds, D/As, LCDs etc. are all being built bytes will be required to be output. This same method with a serial interface to reduce cost, size, pin count, will work for any 93 series device. A 93LC66 was and board area. There are many different serial chosen as the device to write this application note code interfaces on the market used to interface peripherals for, so the following example will be for that particular 2 (I C , Microwire , SPI, for example). One of the serial device. The theory explained below will work for any 93 interfaces that is gaining in popularity is SPI (Serial series device. Peripheral Interface). It is becoming more popular because of its communication speed, simultaneous Since more than 8 bits are required to control a full-duplex communication, and ease of programming. 93LC66, two consecutive bytes are required. Microchip PIC16C64/74 microcontrollers have a built-in High Byte (where the start bit, op code bits, and serial port that can be configured as an SPI port. address MSB reside) Currently, the Microchip Serial EEPROM product line | 0 | 0 | 0 | 0 | SB | OP1 | OP0 | A8 | does not support SPI interface Serial EEPROMs, The High Byte is configured in the following format: SB however it is possible to use the 93 series devices on the is the start bit, OP1 is op code MSB, OP0 is op code SPI port. Any version of Microchip’s 93 series devices LSB, and A8 is the 9th address bit that is required to can be communicated with via the SPI port of a address 512 bytes. The CS can be set before the byte PIC16C64/74. The code for this application note is is output because the leading 0’s output to the 93xxxx written for a Microchip 93LC56/66, but talking to other 93 prevent a start bit from being recognized by the 93xxxx series devices can be accommodated with minor code until the first high bit is sent. changes. See the Theory of Operation section of this application note for more details on how this is Low Byte (8 address LSBs) accomplished. This code was verified by downloading to | A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 | Microchip’s PICMASTER in-circuit emulator (run at full The Low Byte contains A7-A0, which are the rest of the speed with a 10 MHz crystal) and tested to make sure it address bits required to access 512 bytes. writes (polling ready/busy pin to verify write cycle completion) and reads properly. A schematic (Figure 1) Data output from master MUST be set up on the falling is included in this application note to describe exactly edge of the clock so that it can be read from the how the 93LC56/66 was connected to the PIC16C64/74. 93XXXX on the next rising edge. Receiving data from the 93XXXX MUST also happen on the falling edge of The SPI interface was popularized by the Motorola the clock because the data is output from the 93XXXX 68HCXX microcontrollers. Microchip receives many on the rising edge of the clock. THIS REQUIRES THE requests for Motorola assembly code that uses the SPI CLOCK PHASE BIT OF THE SPI PORT TO BE port of the 68HC11 or 68HC05 to talk to Microchip OPPOSITE FOR RECEIVING THAN IT IS FOR serial EEPROMs. Because of this, Microchip has TRANSMITTING. The clock phase needs to be written 68HC11 assembly code to communicate with its toggled between 0 for transmitting data and 1 for 93 series devices via its SPI port. The program was receiving data. See source code for the exact spot downloaded to a 68HC11 evaluation board and tested where the clock phase bit needs to be changed. 1995 Microchip Technology Inc. DS00613A-page 1 Thi d t t d ith F M k 4 0 4 AN613 FIGURE 1: PIC16C74 TO 93LC56/66 SCHEMATIC VDD PIC16C74 VDD RA0/AN0 RA1/AN1 RA2/AN2 MCLR/VPP RA3/AN3 RA4/T0CKI RA5/AN4/SS VSS RB0/INT RB1 OSC1/CLKIN RB2 RB3 OSC2/CLKOUT RB4 10.0 MHz RB5 RB6 RB7 VDD 15pF 15pF 93LC56/66 RC0/T1OSO/T1CKI CS VCC RC1/T1OSI/CCP2 RC2/CCP1 CLK NC RC3/SCK/SCL RC4/SDI/SDA DI ORG RC5/SDO RC6/TX/CK DO VSS RC7/RX/DT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 DS00613A-page 2 1995 Microchip Technology Inc. AN613 FIGURE 2: MOTOROLA 68HC11 TO MICROCHIP 93LC56/66 SCHEMATIC MC68HC11E9 E VDD µ VDD PA0/IC3 System + 0.1 F PA1/IC2 PA2/IC0 Power 4.7µF PA3/OC5/OC1 VSS PA4/OC4/OC1 PA5/0C3/0C1 PA6/0C2/0C1 10MΩ EXTAL PA7/PAI/OC1 XTAL STRB 8.0 MHz STRA PB0 18pF 18pF PB1 PB2 PB3 PB4 4.7kΩ PB5 VDD RESET PB6 PB7 4.7kΩ XIRQ PC0 4.7kΩ PC1 IRQ PC2 PC3 PC4 10kΩ PC5 VDD 4.7kΩ PC6 PC7 93LC56/66 MODB/VSTBY CS VCC PD0/RxD MODA/LIR PD1/TxD CLK NC PD2/MISO PD3/MOSI DI ORG PD4/SCK PD5/SS DO VSS PE0/AN0 PE1/AN1 VRH PE2/AN2 PE3/AN3 PE4/AN4 PE5/AN5 VRL PE6/AN6 PE7/AN7 Note: A pull down resistor is included on the CS pin. It deselects the 93LC56/66, always, except for when CS is driven high by the 68HC11. 1995 Microchip Technology Inc. DS00613A-page 3 AN613 Please check the Microchip BBS for the latest version of the source code. For BBS access information, see Section 6, Microchip Bulletin Board Service information, page 6-3. APPENDIX A: PIC16C64/74 SOURCE CODE ;**************************************************** ; ; To use the SPI port to communicate with 3-wire devices, ; the bytes to be output must be aligned such that the LSB of the ; address is the 8th bit (LSB) of a byte to be output. From there, ; the bits should fill the byte from right to left consecutively. ; This same method will work for any 93xxxx device. A 93LC66 was ; chosen as the device to write this application note code for, ; so the following example will be for that particular device. ; The theory explained below will work for any 93 series device. ; ; Since more than 8 bits are required to control a 93LC66, ; two consecutive bytes are required. ; ; High byte (where start bit, op code bits and address MSB reside) ; ; | 0 | 0 | 0 | 0 | SB | OP1 | OP0 | A8 | ; ; The High Byte is configured in the following format: ; SB is the start bit, OP1 is op code MSB, OP0 is op code LSB, and A8 ; is the 9th address bit that is required to address 512 bytes. The CS ; can be set before the byte is output because the leading 0’s output to ; the 93xxxx prevent a start bit from being recognized by the 93xxxx until ; the first high bit is sent. ; ; Low byte (8 address LSBs) ; ; | A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 | ; ; The Low Byte contains A8-A0, which are address bits required ; to access 512 bytes. ; ; The chip select is set high before sending the first byte out because ; the 93LC66 will not recognize a start bit until both CS and DI are ; high on the rising edge of a clock. ; ; This code is written to use the 16C64/74 SPI port to communicate with a ; Microchip 93LC66. The only other I/O line required besides the SPI port ; pins is a chip select. The ORG pin will be grounded to set up the part ; in x8 mode. ; ; PIN DESCRIPTIONS: ; ; SCK (serial clock) port C, bit 3 ; SDO (serial data out) port C, bit 5 ; SDI (serial data in) port C, bit 4 ; CS (chip select) port C, bit 0 ; ; Transmits from the master MUST happen on the falling edge of the clock ; so they can be read by the 93xxxx on the next rising edge of the clock. ; Receiving from the 93xxx MUST also happen on the falling edge of the ; clock because on the rising edge of the clock, the 93xxxx outputs its bit ; on its DO pin. This requires the CKP bit in the SSPCON register to be set ; to 1 for transmitting data and CKP=0 for receiving data. ; ; This code was written by Keith Pazul on 10/5/94 ; ;********************************************************** ;**************************************************** ; Ram Register Definitions DS00613A-page 4 1995 Microchip Technology Inc. AN613 ;**************************************************** ; ; received bytes from EEPROM memory locations 10h to 13h ; will be stored in RAM registers 20h to 23h. rxdata equ 24h txdata equ 25h addr equ 26h loops equ 27h loops2 equ 28h hibyte equ 29h lobyte equ 2Ah datbyt equ 2Bh ;**************************************************** ; ; Other Definitions ; ;**************************************************** ; ; ;**************************************************** ; Bit Definitions ;**************************************************** ; cs equ 0 sdi equ 4 ;**************************************************** include “c:\mpasm\include\p16cxx.inc” ; register map for PIC16CXX devices org 0x000 ; Reset Vector goto Start ; ;*********************************************************** ; ; This is the transmit/receive routine.