CSEE 3827: Fundamentals of Computer Systems Lecture 18, 19, & 20 April 2009 Martha Kim [email protected] Outline • We will examine two MIPS implementations • A single-cycle version • A pipelined version • Simple subset of MIPS, showing most aspects • Memory reference: lw, sw • Arithmetic/logical: add, sub, and, or, slt • Control transfer: beq, j • CPU performance factors • Instruction count (determined by ISA and compiler) • Cycles per instruction and cycle time (determined by CPU hardware) CSEE 3827, Spring 2009 Martha Kim 2 Instruction Execution • PC → instruction memory, fetch instruction • Register numbers → register file, read registers • Depending on instruction class: • Use ALU to calculate: • Arithmetic or logical result • Memory address for load/store • Branch target address • Access data for load/store • PC ← target address or PC + 4 CSEE 3827, Spring 2009 Martha Kim 3 CPU Overview !DD !DD $ATA 2EGISTER 0# !DDRESS )NSTRUCTION 2EGISTERS !,5 !DDRESS 2EGISTER $ATA )NSTRUCTION MEMORY MEMORY 2EGISTER $ATA 1, Ê {°£Ê Ê >LÃÌÀ>VÌÊ ÛiÜÊ vÊ Ì iÊ «iiÌ>ÌÊ vÊ Ì iÊ *-Ê ÃÕLÃiÌÊ Ã Ü}Ê Ì iÊ >ÀÊvÕVÌ>ÊÕÌÃÊ>`ÊÌ iÊ>ÀÊViVÌÃÊLiÌÜiiÊÌ i°Ê!LLINSTRUCTIONSSTARTBYUSING THEPROGRAMCOUNTERTOSUPPLYTHEINSTRUCTIONADDRESSTOTHEINSTRUCTIONMEMORY!FTERTHEINSTRUCTIONIS FETCHED THEREGISTEROPERANDSUSEDBYANINSTRUCTIONARESPECIlEDBYlELDSOFTHATINSTRUCTION/NCETHE REGISTEROPERANDSHAVEBEENFETCHED THEYCANBEOPERATEDONTOCOMPUTEAMEMORYADDRESSFORALOADOR STORE TOCOMPUTEANARITHMETICRESULTFORANINTEGERARITHMETIC LOGICALINSTRUCTION ORACOMPAREFORA BRANCH )FTHEINSTRUCTIONISANARITHMETIC LOGICALINSTRUCTION THERESULTFROMTHE!,5MUSTBEWRITTENTO AREGISTER)FTHEOPERATIONISALOADORSTORE THE!,5RESULTISUSEDASANADDRESSTOEITHERSTOREAVALUEFROM THEREGISTERSORLOADAVALUEFROMMEMORYINTOTHEREGISTERS4HERESULTFROMTHE!,5ORMEMORYISWRITTEN BACKINTOTHEREGISTERlLE"RANCHESREQUIRETHEUSEOFTHE!,5OUTPUTTODETERMINETHENEXTINSTRUCTION ADDRESS WHICHCOMESEITHERFROMTHE!,5WHERETHE0#ANDBRANCHOFFSETARESUMMED ORFROMANADDER THATINCREMENTSTHECURRENT0#BY4HETHICKLINESINTERCONNECTINGTHEFUNCTIONALUNITSREPRESENTBUSES WHICHCONSISTOFMULTIPLESIGNALS4HEARROWSAREUSEDTOGUIDETHEREADERINKNOWINGHOWINFORMATIONmOWS 3INCESIGNALLINESMAYCROSS WEEXPLICITLYSHOWWHENCROSSINGLINESARECONNECTEDBYTHEPRESENCEOFADOT WHERETHELINESCROSS#OPYRIGHTÚ%LSEVIER )NC!LLRIGHTSRESERVED CSEE 3827, Spring 2009 Martha Kim 4 Can’t just join wires together, use muxes !DD !DD $ATA 2EGISTER 0# !DDRESS )NSTRUCTION 2EGISTERS !,5 !DDRESS 2EGISTER $ATA )NSTRUCTION MEMORY MEMORY 2EGISTER $ATA 1, Ê {°£Ê Ê >LÃÌÀ>VÌÊ ÛiÜÊ vÊ Ì iÊ «iiÌ>ÌÊ vÊ Ì iÊ *-Ê ÃÕLÃiÌÊ Ã Ü}Ê Ì iÊ >ÀÊvÕVÌ>ÊÕÌÃÊ>`ÊÌ iÊ>ÀÊViVÌÃÊLiÌÜiiÊÌ i°Ê!LLINSTRUCTIONSSTARTBYUSING THEPROGRAMCOUNTERTOSUPPLYTHEINSTRUCTIONADDRESSTOTHEINSTRUCTIONMEMORY!FTERTHEINSTRUCTIONIS FETCHED THEREGISTEROPERANDSUSEDBYANINSTRUCTIONARESPECIlEDBYlELDSOFTHATINSTRUCTION/NCETHE REGISTEROPERANDSHAVEBEENFETCHED THEYCANBEOPERATEDONTOCOMPUTEAMEMORYADDRESSFORALOADOR STORE TOCOMPUTEANARITHMETICRESULTFORANINTEGERARITHMETIC LOGICALINSTRUCTION ORACOMPAREFORA BRANCH )FTHEINSTRUCTIONISANARITHMETIC LOGICALINSTRUCTION THERESULTFROMTHE!,5MUSTBEWRITTENTO AREGISTER)FTHEOPERATIONISALOADORSTORE THE!,5RESULTISUSEDASANADDRESSTOEITHERSTOREAVALUEFROM THEREGISTERSORLOADAVALUEFROMMEMORYINTOTHEREGISTERS4HERESULTFROMTHE!,5ORMEMORYISWRITTEN BACKINTOTHEREGISTERlLE"RANCHESREQUIRETHEUSEOFTHE!,5OUTPUTTODETERMINETHENEXTINSTRUCTION ADDRESS WHICHCOMESEITHERFROMTHE!,5WHERETHE0#ANDBRANCHOFFSETARESUMMED ORFROMANADDER THATINCREMENTSTHECURRENT0#BY4HETHICKLINESINTERCONNECTINGTHEFUNCTIONALUNITSREPRESENTBUSES WHICHCONSISTOFMULTIPLESIGNALS4HEARROWSAREUSEDTOGUIDETHEREADERINKNOWINGHOWINFORMATIONmOWS 3INCESIGNALLINESMAYCROSS WEEXPLICITLYSHOWWHENCROSSINGLINESARECONNECTEDBYTHEPRESENCEOFADOT WHERETHELINESCROSS#OPYRIGHTÚ%LSEVIER )NC!LLRIGHTSRESERVED CSEE 3827, Spring 2009 Martha Kim 5 Control "RANCH - U X - !DD !DD U X !,5OPERATION $ATA -EM7RITE 2EGISTER 0# !DDRESS )NSTRUCTION 2EGISTERS !,5 !DDRESS 2EGISTER - :ERO $ATA )NSTRUCTION U X MEMORY MEMORY 2EGISTER 2EG7RITE $ATA -EM2EAD #ONTROL 1, Ê{°ÓÊ / iÊL>ÃVÊ«iiÌ>ÌÊvÊÌ iÊ*-ÊÃÕLÃiÌ]ÊVÕ`}ÊÌ iÊiViÃÃ>ÀÞÊÕÌ«iÝÀÃÊ>`ÊVÌÀÊiÃ°Ê 4HETOPMULTIPLEXORh-UXv CONTROLSWHATVALUEREPLACESTHE0#0# ORTHEBRANCHDESTINATIONADDRESS THEMULTIPLEXORISCONTROLLED BYTHEGATETHATh!.$SvTOGETHERTHE:EROOUTPUTOFTHE!,5ANDACONTROLSIGNALTHATINDICATESTHATTHEINSTRUCTIONISABRANCH4HEMIDDLE MULTIPLEXOR WHOSEOUTPUTRETURNSTOTHEREGISTERlLE ISUSEDTOSTEERTHEOUTPUTOFTHE!,5INTHECASEOFANARITHMETIC LOGICALINSTRUCTION ORTHEOUTPUTOFTHEDATAMEMORYINTHECASEOFALOAD FORWRITINGINTOTHEREGISTERlLE&INALLY THEBOTTOMMOSTMULTIPLEXORISUSEDTO DETERMINEWHETHERTHESECOND!,5INPUTISFROMTHEREGISTERSFORANARITHMETIC LOGICALINSTRUCTION/2ABRANCH ORFROMTHEOFFSETlELDOF THEINSTRUCTIONFORALOADORSTORE 4HEADDEDCONTROLLINESARESTRAIGHTFORWARDANDDETERMINETHEOPERATIONPERFORMEDATTHE!,5 WHETHER THEDATAMEMORYSHOULDREADORWRITE ANDWHETHERTHEREGISTERSSHOULDPERFORMAWRITEOPERATION4HECONTROLLINESARESHOWNINCOLORTO MAKETHEMEASIERTOSEE#OPYRIGHTÚ%LSEVIER )NC!LLRIGHTSRESERVED CSEE 3827, Spring 2009 Martha Kim 6 MIPS Datapath Combinational Elements • AND gate (Y = A & B) • Adder (Y = A + B) A A Y B + Y B • Multiplexer (Y = S ? A : B) • Arithmetic/Logic Unit (ALU) (Y = F(A,B)) A Y B A ALU Y S B F CSEE 3827, Spring 2009 Martha Kim 8 Clocking Methodology Combinational logic transforms data during clock cycles. Longest combinational delay determines clock period. 3TATE 3TATE ELEMENT #OMBINATIONALLOGIC ELEMENT #LOCKCYCLE 1, Ê{°ÎÊ L>Ì>Ê}V]ÊÃÌ>ÌiÊiiiÌÃ]Ê>`ÊÌ iÊVVÊ>ÀiÊVÃiÞÊÀi>Ìi`°Ê)NA SYNCHRONOUSDIGITALSYSTEM THECLOCKDETERMINESWHENELEMENTSWITHSTATEWILLWRITEVALUESINTOINTERNAL STORAGE!NYINPUTSTOASTATEELEMENTMUSTREACHASTABLEVALUETHATIS HAVEREACHEDAVALUEFROMWHICHTHEY WILLNOTCHANGEUNTILAFTERTHECLOCKEDGE BEFORETHEACTIVECLOCKEDGECAUSESTHESTATETOBEUPDATED!LLSTATE ELEMENTSINTHISCHAPTER INCLUDINGMEMORY AREASSUMEDTOBEEDGE TRIGGERED#OPYRIGHTÚ%LSEVIER )NC !LLRIGHTSRESERVED 3TATE #OMBINATIONALLOGIC ELEMENT 1, Ê{°{Ê Êi`}iÌÀ}}iÀi`ÊiÌ `}ÞÊ>ÜÃÊ>ÊÃÌ>ÌiÊiiiÌÊÌÊLiÊÀi>`Ê>`ÊÜÀÌ ÌiÊÊÌ iÊÃ>iÊVVÊVÞViÊÜÌ ÕÌÊVÀi>Ì}Ê>ÊÀ>ViÊÌ >ÌÊVÕ`Êi>`ÊÌÊ`iÌiÀ>ÌiÊ`>Ì>Ê Û>Õið/FCOURSE THECLOCKCYCLESTILLMUSTBELONGENOUGHSOTHATTHEINPUTVALUESARESTABLEWHENTHE ACTIVECLOCKEDGEOCCURS&EEDBACKCANNOTOCCURWITHINONECLOCKCYCLEBECAUSEOFTHEEDGE TRIGGEREDUPDATE OFTHESTATEELEMENT)FFEEDBACKWERE POSSIBLE THISDESIGNCOULDNOTWORKPROPERLY /URDESIGNSINTHIS CHAPTERANDTHENEXTRELYONTHEEDGE TRIGGEREDTIMINGMETHODOLOGYANDONSTRUCTURESLIKETHEONESHOWN INTHISlGURE#OPYRIGHTÚ%LSEVIER )NC!LLRIGHTSRESERVED CSEE 3827, Spring 2009 Martha Kim 9 Building a datapath incrementally • Datapath: elements that process data and addresses in the CPU • Datapath will execute one instruction in one clock cycle • Each datapath element can only do one function at a time • Hence, we need separate instruction and data memories • Use multiplexers where alternate data sources are used for different instructions CSEE 3827, Spring 2009 Martha Kim 10 Instruction Fetch • Fetch Instruction contained in PC register from memory • Compute PC + 4 for next instruction )NSTRUCTION ADDRESS )NSTRUCTION 0# !DD 3UM )NSTRUCTION MEMORY A)NSTRUCTIONMEMORY B0ROGRAMCOUNTER C!DDER 1, Ê {°xÊ /ÜÊ ÃÌ>ÌiÊ iiiÌÃÊ >ÀiÊ ii`i`Ê ÌÊ ÃÌÀiÊ >`Ê >VViÃÃÊ ÃÌÀÕVÌÃ]Ê >`Ê >Ê >``iÀÊÃÊii`i`ÊÌÊV«ÕÌiÊÌ iÊiÝÌÊÃÌÀÕVÌÊ>``ÀiÃðÊ4HESTATEELEMENTSARETHEINSTRUCTION MEMORY AND THE PROGRAM COUNTER 4HE INSTRUCTION MEMORYNEED ONLY PROVIDE READ ACCESS BECAUSE THE DATAPATHDOESNOTWRITEINSTRUCTIONS3INCETHEINSTRUCTIONMEMORYONLYREADS WETREATITASCOMBINATIONAL LOGICTHEOUTPUTATANYTIMEREmECTSTHECONTENTSOFTHELOCATIONSPECIlEDBYTHEADDRESSINPUT ANDNOREAD CONTROLSIGNALISNEEDED7EWILLNEEDTOWRITETHEINSTRUCTIONMEMORYWHENWELOADTHEPROGRAMTHISIS NOTHARDTOADD ANDWEIGNOREITFORSIMPLICITY 4HEPROGRAMCOUNTERISA BITREGISTERTHATISWRITTENATTHE ENDOFEVERYCLOCKCYCLEANDTHUSDOESNOTNEEDAWRITECONTROLSIGNAL4HEADDERISAN!,5WIREDTOALWAYS ADDITSTWO BITINPUTSANDPLACETHESUMONITSOUTPUT#OPYRIGHTÚ%LSEVIER )NC!LLRIGHTSRESERVED CSEE 3827, Spring 2009 Martha Kim 11 Part 1: Instruction Fetch !DD 2EAD 0# ADDRESS )NSTRUCTION )NSTRUCTION MEMORY 1, Ê{°ÈÊ Ê«ÀÌÊvÊÌ iÊ`>Ì>«>Ì ÊÕÃi`ÊvÀÊviÌV }ÊÃÌÀÕVÌÃÊ>`ÊVÀiiÌ}Ê Ì iÊ«À}À>ÊVÕÌiÀ°Ê4HEFETCHEDINSTRUCTIONISUSEDBYOTHERPARTSOFTHEDATAPATH#OPYRIGHTÚ %LSEVIER )NC!LLRIGHTSRESERVED CSEE 3827, Spring 2009 Martha Kim 12 R-Format Instructions • Read two register operands • Perform arithmetic/logical operation • Write register result 2EAD !,5OPERATION REGISTER 2EAD 2EGISTER 2EAD DATA NUMBERS REGISTER :ERO $ATA !,5 2EGISTERS !,5 7RITE RESULT REGISTER 2EAD 7RITE DATA $ATA $ATA 2EG7RITE A2EGISTERS B!,5 1, Ê {°ÇÊ / iÊ ÌÜÊ iiiÌÃÊ ii`i`Ê ÌÊ «iiÌÊ ,vÀ>ÌÊ 1Ê «iÀ>ÌÃÊ >ÀiÊ Ì iÊ Ài}ÃÌiÀÊwÊiÊ>`ÊÌ iÊ1°Ê4HEREGISTERlLECONTAINSALLTHEREGISTERSANDHASTWOREADPORTSANDONEWRITE PORT4HEDESIGNOFMULTIPORTEDREGISTERlLESISDISCUSSEDIN3ECTION#OF !PPENDIX#4HEREGISTERlLE ALWAYSOUTPUTSTHECONTENTSOFTHEREGISTERSCORRESPONDINGTOTHE2EADREGISTERINPUTSONTHEOUTPUTSNO OTHERCONTROLINPUTSARENEEDED)NCONTRAST AREGISTERWRITEMUSTBEEXPLICITLYINDICATEDBYASSERTINGTHE WRITECONTROLSIGNAL2EMEMBERTHATWRITESAREEDGE TRIGGERED SOTHATALLTHEWRITEINPUTSIE THEVALUETO BEWRITTEN THEREGISTERNUMBER ANDTHEWRITECONTROLSIGNAL MUSTBEVALIDATTHECLOCKEDGE3INCEWRITESTO THEREGISTERlLEAREEDGE TRIGGERED OURDESIGNCANLEGALLYREADANDWRITETHESAMEREGISTERWITHINACLOCKCYCLE THEREADWILLGETTHEVALUEWRITTENINANEARLIERCLOCKCYCLE WHILETHEVALUEWRITTENWILLBEAVAILABLETOAREADIN ASUBSEQUENTCLOCKCYCLE4HEINPUTSCARRYINGTHEREGISTERNUMBERTOTHEREGISTERlLEAREALLBITSWIDE WHEREAS THELINESCARRYINGDATAVALUESAREBITSWIDE4HEOPERATIONTOBEPERFORMEDBYTHE!,5ISCONTROLLEDWITH THE!,5OPERATIONSIGNAL WHICHWILLBEBITSWIDE USINGTHE!,5DESIGNEDIN !PPENDIX#7EWILL USETHE:ERODETECTIONOUTPUTOFTHE!,5SHORTLYTOIMPLEMENTBRANCHES4HEOVERmOWOUTPUTWILLNOTBE