TMS320DM35x Digital Media System-on-Chip (DMSoC) Timer/Watchdog Timer Reference Guide Literature Number: SPRUEE5A May 2006–Revised September 2007 2 SPRUEE5A–May 2006–Revised September 2007 Submit Documentation Feedback Contents Preface ............................................................................................................................... 6 1 Introduction................................................................................................................ 9 1.1 Purpose of the Peripheral....................................................................................... 9 1.2 Features ........................................................................................................... 9 1.3 Functional Block Diagram ..................................................................................... 10 1.4 Industry Standard Compatibility Statement ................................................................. 10 2 Architecture – General-Purpose Timer Mode ................................................................ 10 2.1 Backward Compatible Mode (Timer 3 Only) ................................................................ 10 2.2 Clock Control.................................................................................................... 11 2.3 Signal Descriptions ............................................................................................. 12 2.4 Timer Modes .................................................................................................... 13 2.5 Timer Operation Boundary Conditions....................................................................... 20 2.6 General-Purpose Timer Power Management............................................................... 21 3 Architecture – Watchdog Timer Mode .......................................................................... 21 3.1 Watchdog Timer ................................................................................................ 21 3.2 Watchdog Timer Mode Restrictions.......................................................................... 22 3.3 Watchdog Timer Mode Operation ............................................................................ 22 3.4 Watchdog Timer Register Write Protection ................................................................. 24 3.5 Watchdog Timer Power Management ....................................................................... 24 4 Reset Considerations................................................................................................. 24 4.1 Software Reset Considerations............................................................................... 24 4.2 Hardware Reset Considerations.............................................................................. 24 5 Interrupt Support....................................................................................................... 24 6 EDMA Event Support ................................................................................................. 25 7 RTO Event Support (Timer 3 only) ............................................................................... 25 8 Interrupt/EDMA/RTO Event Generation Control and Status (Timer 3 only) ........................ 25 9 Power Management ................................................................................................... 25 10 Emulation Considerations .......................................................................................... 26 11 Registers.................................................................................................................. 27 11.1 Peripheral Identification Register 12 (PID12) ............................................................... 27 11.2 Emulation Management Register (EMUMGT) .............................................................. 29 11.3 Timer Counter Registers (TIM12 and TIM34)............................................................... 30 11.4 Timer Period Registers (PRD12 and PRD34) .............................................................. 31 11.5 Timer Control Register (TCR)................................................................................. 32 11.6 Timer Global Control Register (TGCR) ...................................................................... 34 11.7 Watchdog Timer Control Register (WDTCR) ............................................................... 35 11.8 Timer Reload Register 12 Register (REL12) ............................................................... 35 11.9 Timer Reload Register 34 Register (REL34) ............................................................... 35 11.10 Timer Capture Register 12 Register (CAP12).............................................................. 36 11.11 Timer Capture Register 34 Register (CAP34).............................................................. 36 11.12 Timer Interrupt Control and Status Register (INTCTL_STAT) ........................................... 36 SPRUEE5A–May 2006–Revised September 2007 Table of Contents 3 Submit Documentation Feedback List of Figures 1 Timer Block Diagram ...................................................................................................... 10 2 Timer Clock Source Block Diagram...................................................................................... 11 3 64-Bit Timer Mode Block Diagram ....................................................................................... 13 4 Dual 32-Bit Timers Chained Mode Block Diagram .................................................................... 15 5 Dual 32-Bit Timers Chained Mode Example............................................................................ 15 6 Dual 32-Bit Timers Unchained Mode Block Diagram.................................................................. 17 7 Dual 32-Bit Timers Unchained Mode Example......................................................................... 18 8 32-Bit Timer Counter Overflow Example................................................................................ 21 9 Watchdog Timer Mode Block Diagram .................................................................................. 22 10 Watchdog Timer Operation State Diagram ............................................................................. 23 11 Peripheral Identification Register 12 (PID12)........................................................................... 27 12 Emulation Management Register (EMUMGT).......................................................................... 29 13 Timer Counter Register 12 (TIM12)...................................................................................... 30 14 Timer Counter Register 34 (TIM34)...................................................................................... 30 15 Timer Period Register 12 (PRD12) ...................................................................................... 31 16 Timer Period Register 34 (PRD34) ...................................................................................... 31 17 Timer Control Register (TCR) ............................................................................................ 32 18 Timer Global Control Register (TGCR).................................................................................. 34 19 Watchdog Timer Control Register (WDTCR) ........................................................................... 35 20 Timer Reload Register 12 (REL12) Register ........................................................................... 35 21 Timer Reload Register 34 Register (REL34) ........................................................................... 35 22 Timer Capture Register 12 Register (CAP12).......................................................................... 36 23 Timer Capture Register 34 Register (CAP34).......................................................................... 36 24 Timer Interrupt Control and Status Register (INTCTL_STAT) ....................................................... 37 4 List of Figures SPRUEE5A–May 2006–Revised September 2007 Submit Documentation Feedback List of Tables 1 Supported Timer Features by Instantiation............................................................................... 9 2 Supported Timer Clock Sources ......................................................................................... 11 3 Timer Clock Source Selection ............................................................................................ 11 4 64-Bit Timer Configurations............................................................................................... 14 5 32-Bit Timer Chained Mode Configurations ............................................................................ 16 6 32-Bit Timer Unchained Mode Configurations.......................................................................... 19 7 Counter and Period Registers Used in GP Timer Modes............................................................. 20 8 Timer Interrupts Generated ............................................................................................... 24 9 Timer EDMA Events Generated.......................................................................................... 25 10 Timer Emulation Modes Selection ....................................................................................... 26 11 TMR Global Registers ..................................................................................................... 27 12 Peripheral Identification