Product Sample & Technical Tools & Support & Reference Folder Buy Documents Software Community Design AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 SPRS717J –OCTOBER 2011–REVISED APRIL 2016 AM335x Sitara™ Processors 1 Device Overview 1.1 Features 1 • Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit – Supports Protocols such as EtherCAT®, RISC Processor PROFIBUS, PROFINET, EtherNet/IP™, and – NEON™ SIMD Coprocessor More – 32KB of L1 Instruction and 32KB of Data Cache – Two Programmable Real-Time Units (PRUs) With Single-Error Detection (Parity) • 32-Bit Load/Store RISC Processor Capable – 256KB of L2 Cache With Error Correcting Code of Running at 200 MHz (ECC) • 8KB of Instruction RAM With Single-Error – 176KB of On-Chip Boot ROM Detection (Parity) – 64KB of Dedicated RAM • 8KB of Data RAM With Single-Error – Emulation and Debug - JTAG Detection (Parity) – Interrupt Controller (up to 128 Interrupt • Single-Cycle 32-Bit Multiplier With 64-Bit Requests) Accumulator • On-Chip Memory (Shared L3 RAM) • Enhanced GPIO Module Provides Shift- In/Out Support and Parallel Latch on – 64KB of General-Purpose On-Chip Memory External Signal Controller (OCMC) RAM – 12KB of Shared RAM With Single-Error – Accessible to All Masters Detection (Parity) – Supports Retention for Fast Wakeup – Three 120-Byte Register Banks Accessible by • External Memory Interfaces (EMIF) Each PRU – mDDR(LPDDR), DDR2, DDR3, DDR3L – Interrupt Controller (INTC) for Handling System Controller: Input Events • mDDR: 200-MHz Clock (400-MHz Data – Local Interconnect Bus for Connecting Internal Rate) and External Masters to the Resources Inside • DDR2: 266-MHz Clock (532-MHz Data Rate) the PRU-ICSS • DDR3: 400-MHz Clock (800-MHz Data Rate) – Peripherals Inside the PRU-ICSS: • DDR3L: 400-MHz Clock (800-MHz Data • One UART Port With Flow Control Pins, Rate) Supports up to 12 Mbps • 16-Bit Data Bus • One Enhanced Capture (eCAP) Module • 1GB of Total Addressable Space • Two MII Ethernet Ports that Support • Supports One x16 or Two x8 Memory Device Industrial Ethernet, such as EtherCAT Configurations • One MDIO Port – General-Purpose Memory Controller (GPMC) • Power, Reset, and Clock Management (PRCM) • Flexible 8-Bit and 16-Bit Asynchronous Module Memory Interface With up to Seven Chip – Controls the Entry and Exit of Stand-By and Selects (NAND, NOR, Muxed-NOR, SRAM) Deep-Sleep Modes • Uses BCH Code to Support 4-, 8-, or 16-Bit – Responsible for Sleep Sequencing, Power ECC Domain Switch-Off Sequencing, Wake-Up • Uses Hamming Code to Support 1-Bit ECC Sequencing, and Power Domain Switch-On – Error Locator Module (ELM) Sequencing • Used in Conjunction With the GPMC to – Clocks Locate Addresses of Data Errors from • Integrated 15- to 35-MHz High-Frequency Syndrome Polynomials Generated Using a Oscillator Used to Generate a Reference BCH Algorithm Clock for Various System and Peripheral • Supports 4-, 8-, and 16-Bit per 512-Byte Clocks Block Error Location Based on BCH • Supports Individual Clock Enable and Algorithms Disable Control for Subsystems and • Programmable Real-Time Unit Subsystem and Peripherals to Facilitate Reduced Power Industrial Communication Subsystem (PRU-ICSS) Consumption 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 SPRS717J –OCTOBER 2011–REVISED APRIL 2016 www.ti.com • Five ADPLLs to Generate System Clocks • Supports Digital Audio Interface (MPU Subsystem, DDR Interface, USB and Transmission (SPDIF, IEC60958-1, and Peripherals [MMC and SD, UART, SPI, I2C], AES-3 Formats) L3, L4, Ethernet, GFX [SGX530], LCD Pixel • FIFO Buffers for Transmit and Receive (256 Clock) Bytes) – Power – Up to Six UARTs • Two Nonswitchable Power Domains (Real- • All UARTs Support IrDA and CIR Modes Time Clock [RTC], Wake-Up Logic • All UARTs Support RTS and CTS Flow [WAKEUP]) Control • Three Switchable Power Domains (MPU • UART1 Supports Full Modem Control Subsystem [MPU], SGX530 [GFX], – Up to Two Master and Slave McSPI Serial Peripherals and Infrastructure [PER]) Interfaces • Implements SmartReflex™ Class 2B for • Up to Two Chip Selects Core Voltage Scaling Based On Die Temperature, Process Variation, and • Up to 48 MHz Performance (Adaptive Voltage Scaling – Up to Three MMC, SD, SDIO Ports [AVS]) • 1-, 4- and 8-Bit MMC, SD, SDIO Modes • Dynamic Voltage Frequency Scaling (DVFS) • MMCSD0 has Dedicated Power Rail for • Real-Time Clock (RTC) 1.8‑V or 3.3-V Operation – Real-Time Date (Day-Month-Year-Day of Week) • Up to 48-MHz Data Transfer Rate and Time (Hours-Minutes-Seconds) Information • Supports Card Detect and Write Protect – Internal 32.768-kHz Oscillator, RTC Logic and • Complies With MMC4.3, SD, SDIO 2.0 1.1-V Internal LDO Specifications – Independent Power-on-Reset – Up to Three I2C Master and Slave Interfaces (RTC_PWRONRSTn) Input • Standard Mode (up to 100 kHz) – Dedicated Input Pin (EXT_WAKEUP) for • Fast Mode (up to 400 kHz) External Wake Events – Up to Four Banks of General-Purpose I/O – Programmable Alarm Can be Used to Generate (GPIO) Pins Internal Interrupts to the PRCM (for Wakeup) or • 32 GPIO Pins per Bank (Multiplexed With Cortex-A8 (for Event Notification) Other Functional Pins) – Programmable Alarm Can be Used With • GPIO Pins Can be Used as Interrupt Inputs External Output (PMIC_POWER_EN) to Enable (up to Two Interrupt Inputs per Bank) the Power Management IC to Restore Non-RTC – Up to Three External DMA Event Inputs that can Power Domains Also be Used as Interrupt Inputs • Peripherals – Eight 32-Bit General-Purpose Timers – Up to Two USB 2.0 High-Speed OTG Ports • DMTIMER1 is a 1-ms Timer Used for With Integrated PHY Operating System (OS) Ticks – Up to Two Industrial Gigabit Ethernet MACs (10, • DMTIMER4–DMTIMER7 are Pinned Out 100, 1000 Mbps) – One Watchdog Timer • Integrated Switch – SGX530 3D Graphics Engine • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces • Tile-Based Architecture Delivering up to 20 Million Polygons per Second • Ethernet MACs and Switch Can Operate Independent of Other Functions • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel • IEEE 1588v2 Precision Time Protocol (PTP) and Vertex Shader Functionality – Up to Two Controller-Area Network (CAN) Ports • Advanced Shader Feature Set in Excess of • Supports CAN Version 2 Parts A and B Microsoft VS3.0, PS3.0, and OGL2.0 – Up to Two Multichannel Audio Serial Ports • Industry Standard API Support of Direct3D (McASPs) Mobile, OGL-ES 1.1 and 2.0, OpenVG 1.0, • Transmit and Receive Clocks up to 50 MHz and OpenMax • Up to Four Serial Data Pins per McASP Port • Fine-Grained Task Switching, Load With Independent TX and RX Clocks Balancing, and Power Management • Supports Time Division Multiplexing (TDM), • Advanced Geometry DMA-Driven Operation Inter-IC Sound (I2S), and Similar Formats for Minimum CPU Interaction 2 Device Overview Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: AM3359 AM3358 AM3357 AM3356 AM3354 AM3352 AM3351 AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351 www.ti.com SPRS717J –OCTOBER 2011–REVISED APRIL 2016 • Programmable High-Quality Image Anti- – Up to Three 32-Bit Enhanced Quadrature Aliasing Encoder Pulse (eQEP) Modules • Fully Virtualized Memory Addressing for OS • Device Identification Operation in a Unified Memory Architecture – Contains Electrical Fuse Farm (FuseFarm) of – LCD Controller Which Some Bits are Factory Programmable • Up to 24-Bit Data Output; 8 Bits per Pixel • Production ID (RGB) • Device Part Number (Unique JTAG ID) • Resolution up to 2048 × 2048 (With • Device Revision (Readable by Host ARM) Maximum 126-MHz Pixel Clock) • Debug Interface Support • Integrated LCD Interface Display Driver – JTAG and cJTAG for ARM (Cortex-A8 and (LIDD) Controller PRCM), PRU-ICSS Debug • Integrated Raster Controller – Supports Device Boundary Scan • Integrated DMA Engine to Pull Data from the – Supports IEEE 1500 External Frame Buffer Without Burdening the • DMA Processor via Interrupts or a Firmware Timer – On-Chip Enhanced DMA Controller (EDMA) has • 512-Word Deep Internal FIFO Three Third-Party Transfer Controllers (TPTCs) • Supported Display Types: and One Third-Party Channel Controller – Character Displays - Uses LIDD (TPCC), Which Supports up to 64 Controller to Program these Displays Programmable Logical Channels and Eight – Passive Matrix LCD Displays - Uses LCD QDMA Channels. EDMA is Used for: Raster Display Controller to Provide • Transfers to and from On-Chip Memories Timing and Data for Constant Graphics • Transfers to and from External Storage Refresh to a Passive Display (EMIF, GPMC, Slave Peripherals) – Active Matrix LCD Displays - Uses • Inter-Processor Communication (IPC) External Frame Buffer Space and the – Integrates Hardware-Based Mailbox for IPC and Internal DMA Engine to Drive Streaming Spinlock for Process Synchronization Between Data to the Panel Cortex-A8, PRCM, and PRU-ICSS – 12-Bit Successive Approximation Register • Mailbox Registers that Generate Interrupts (SAR) ADC – Four Initiators (Cortex-A8, PRCM, PRU0, • 200K Samples per Second PRU1) • Input can be Selected from any of the Eight • Spinlock has 128 Software-Assigned Lock Analog Inputs Multiplexed Through an 8:1 Registers Analog Switch • Security • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen – Crypto Hardware Accelerators (AES,