A Fully-Integrated Four-way Outphasing Architecture in Heterogeneously Integrated CMOS/GaN Process Technologies Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy in the Graduate School of The Ohio State University By Matthew LaRue, B.S.E.E., M.S. Graduate Program in Electrical and Computer Engineering The Ohio State University 2018 Dissertation Committee: Dr. Waleed Khalil, Advisor Dr. Ayman Fayed Dr. Steven Bibyk c Copyright by Matthew LaRue 2018 Abstract The growth of cellular and wireless communications over the last two decades has led to unprecedented congestion of the radio frequency (RF) spectrum. New frequency bands and bandwidth allocations are constantly being opened up to allevi- ate this congestion, but the demand for wireless data is increasing faster than spec- trum availability. Despite fundamental hardware limitations, the complex and rapidly changing wireless environment necessitates three key requirements for RF transmit- ter: frequency-agility, capability of transmitting complex modulation schemes, and power efficiency. In this work, a four-way outphasing architecture is developed for the generation of complex modulated waveforms across a wide RF frequency range. This proposed architecture offers an ACLR improvement equivalent to a 2-bit phase resolution in- crease compared to traditional two-way outphasing architectures. In addition, this architecture is more resilient to PA amplitude and timing mismatch. This architecture is implemented in DARPA's Diverse Accessible Heterogeneous Integration (DAHI) process technology, featuring the heterogeneous integration of 45nm CMOS SOI and 0.2 µm GaN process technologies. The fabricated transmitter achieves greater than 33 dBm output power and a peak transmitter efficiency of greater than 41%. ii I dedicate this work to my fianc´eeRachel for being by my side throughout my PhD. iii Acknowledgments I would like to thank my parents for always believing in me, supporting my edu- cation, and providing me with guidance as I face difficult decisions in life. To all my friends and family, thank you for all the support you have given me over the years. To all of the members of my research group, thank you for the sharing of technical knowledge and camaraderie over the years. Thank you Dr. Shane Smith for all the help you have been. I would especially like to thank Dr. Jamin McCue and Dr. Lucas Duncan for all they time they took to teach me how to design circuits and for providing an example for me to follow as I advanced through my education. Thank you to the researchers at the Air Force Research Labs for all the assistance you provided for my research. Thank you to DARPA, Air Force Office of Scientific Research, and the NASA Space Technology Research Fellowship for funding and supporting my research. To my professors at Valparaiso University: Dr. Will, Dr. Tougaw, Dr. Budnik, Dr. Hart, Dr. Kraft, Dr, Johnson, and Dr. Olejniczak. Thank you for providing me with strong fundamentals in electrical engineering and encouraging my pursuit of education and learning. There are two individuals I like to specifically thank for what they have done for me. The first is Dr. Brian Dupaix. His technical guidance throughout the duration iv of my time at Ohio State has helped me navigate my research and all the aspects of circuit design. I would also like to thank him for all the personal support and guidance he has offered me over the years. Finally, I would like to thank my advisor, Dr. Waleed Khalil. He saw my potential even when I knew next to nothing about circuit design and has spent countless hours over the past 6 years to help me realize this potential. Thank you for setting a high standard for technical knowledge and quality of work that I will strive to meet throughout my career. To all the people that directly and indirectly contributed to my work that I have forgotten to mention, thank you for your contributions. {Thank You. v Vita 2012 . .B.S.E.E., Vaplaraiso University 2012-2016 . NASA Space Technology Research Fellow 2016-2017 . Ohio State University Fellow 2017 . .M.S., The Ohio State University 2017-present . .Graduate Research Associate, The Ohio State University Publications Research Publications M. LaRue, T. Barton, M. Belz, et al \A Multifunction Transmitter based on a Fully-Digital CMOS/GaN Architecture in DAHI Technology". GOMACTech, March 2018. L. Duncan, B. Dupaix, M. LaRue, et al \A 10b DC-to-20GHz Multiple-Return-to- Zero DAC with >48dB SFDR". IEEE Journal of Solid-State Circuits, Nov. 2017. M. LaRue, B. Dupaix, S. Rashid, et al \A Fully-Integrated S/C Transmitter in 45nm CMOS/0.2µm GaN Heterogeneous Technology". IEEE Compound Semiconductor IC Symposium, Oct. 2017. L. Duncan, B. Dupaix, M. LaRue, et al \A 10b DC-to-20GHz Multiple-Return-to- Zero DAC with >48dB SFDR". International Solid-State Circuits Conference, Feb. 2017. vi S. Rashid, B. Dupaix, M. LaRue, et al \A Wide-Band Complementary Digital Driver for Pulse Modulated Single-Ended and Differential S/C Band Class-E PAs in 130nm GaAs Technoogy". IEEE Compound Semiconductor IC Symposium, Oct. 2016. E. Alwan, S. Balasubramanian, M. LaRue, et al \Coding-Based Ultra-Wideband Digital Beamformer with Significant Hardware Reduction". Springer Journal of Analog Integrated Circuits and Signal Processing, July 2013. M. LaRue, D. Tougaw, J. WIll \Stray Charge in Quantum-dot Cellular Automata: A Validation of the Intercellular Hartree Approximation". IEEE Transactions of Nanotechnology, March 2013. Fields of Study Major Field: Electrical and Computer Engineering Specialization: Analog and RF Electronics vii Table of Contents Page Abstract . ii Dedication . iii Acknowledgments . iv Vita . vi List of Tables . xi List of Figures . xii 1. Introduction . 1 1.1 Transmitter Architectures . 2 1.1.1 Analog Transmitter Architectures . 3 1.1.2 Outphasing Transmitter Architectures . 6 1.2 Heterogeneous Integration . 8 1.3 Research Overview . 10 1.4 Outline . 11 2. Modulation . 12 2.1 SOQPSK . 12 2.1.1 SOQPSK Overview . 13 2.1.2 SOQPSK Specifications . 17 2.2 64-QAM OFDM - LTE . 19 2.2.1 LTE Overview . 20 2.2.2 LTE Specifications . 22 viii 3. Outphasing . 25 3.1 Outphasing History . 25 3.2 Outphasing Overview . 28 3.2.1 Two-way Outphasing Overview . 28 3.2.2 Four-way Outphasing Overview . 31 3.2.3 Receiver Systems . 35 3.3 Recent Advances . 35 3.3.1 Digital Phase Modulators . 37 3.3.2 Four-way Non-isolating Outphasing Combiners . 43 3.4 Outphasing Performance . 45 3.4.1 Outphasing Quantization . 46 3.4.2 Outphasing Power Efficiency . 49 3.4.3 PA and Timing Mismatch . 51 3.4.4 Summary . 56 4. Phase 1 Implementation . 57 4.1 Architecture . 58 4.2 Packaging and Measurement . 59 4.2.1 Packaging . 59 4.2.2 Measured Results . 62 4.3 Comparison and Key Takeaways . 75 5. Phase 2 Implementation . 77 5.1 Phase Modulator Implementation . 77 5.1.1 Reconfigurable DLL . 80 5.1.2 Glitch-Free Multiplexer . 83 5.1.3 Fine Delay . 86 5.1.4 Very-Fine Delay . 87 5.2 Amplification Implementation . 89 5.2.1 CMOS to GaN Driver . 90 5.2.2 Three-stage GaN PA . 92 5.3 Packaging and Measurement . 93 5.4 Conclusions and Takeaways . 96 6. Conclusions and Future Work . 98 6.1 Work Summary and Conclusions . 98 6.2 Future Work . 99 6.3 Final Thoughts . 100 ix Bibliography . 101 x List of Tables Table Page 1.1 Standard RF frequency bands [1] . 10 2.1 Comparison of SOQPSK and 64-QAM LTE . 24 3.1 Comparison of Chireix and LINC outphasing . 28 3.2 Time mismatch percent to time mismatch in picoseconds conversion at various frequencies . 55 3.3 Outphasing transmitter 20 MHz 64-QAM LTE simulation results . 56 4.1 Transmitter implementation overview . 57 4.2 Phase 1 IC packaging and testing overview . 62 4.3 Measured transmitter power breakdown . 64 4.4 Test condition overview for different PA measurements . 65 4.5 Measured single-channel and combined PA performance . 69 4.6 Measured modulated outphasing performance . 70 4.7 Performance comparison of Phase 1 IC to recent works . 75 5.1 Transmitter implementation overview . 78 5.2 Phase 2 IC packaging and testing overview . 96 xi List of Figures Figure Page 1.1 Simplified a) linear and b) nonlinear PA operation . 2 1.2 Block diagrams for a) Homodyne, b) envelope tracking, and c) polar transmitter architectures . 5 1.3 Outphasing transmitter block diagram . 6 1.4 Outphasing vectors showing a) in-phase and b) out-of-phase vector addition . 7 1.5 a) DAHI cross-section showing thermal and electrical heterogeneous in- terconnects (HICs) thermal dissipation paths and b) scanning electron microscope image of InP HIC from [2] . 9 1.6 Transmitter block diagram showing heterogeneous interconnects (HICs) between the integrated dies . 9 2.1 Block diagram for a phase-quantized SOQPSK transmitter . 14 2.2 SOQPSK pulse-shaping filter phase response . 14 2.3 SOQPSK pulse-shaping filter phase response . 16 2.4 3-bit phase-quantized 20 Mbps SOQPSK signal spectral components . 16 2.5 20 Mbps SOQPSK spectrum for 2-8-bit phase quantization showing 1st and 2nd adjacent frequency bands . 18 2.6 Simulated ACLR1 and ACLR2 for 20 Mbps SOQPSK waveform . 19 xii 2.7 a) Wideband single-carrier vs b) multiple orthogonal narrowband sub- carriers . 20 2.8 Block diagram for 64-QAM OFDM LTE transmitter . 21 2.9 Simulated spectrum for 20 MHz 64-QAM LTE waveform . 22 2.10 Vectors demonstrating EVM concept . 23 3.1 Chireix outphasing concept from original 1935 publication [3] . 26 3.2 LINC outphasing concept from 1974 publication [4] . 27 3.3 Polar and Cartesian form relationship .