US007 146585B2 (12) United States Patent (10) Patent No.: US 7,146,585 B2 Blodgett (45) Date of Patent: Dec. 5, 2006 (54) PROGRAMMABLE ELEMENT LATCH (56) References Cited CIRCUIT U.S. PATENT DOCUMENTS (75) Inventor: Greg A. Blodgett, Nampa, ID (US) 5,110,754 A * 5/1992 Lowrey et al. ............. 438,386 5,631,862 A 5/1997 Cutter et al. (73) Assignee: Micron Technology, Inc., Boise, ID 5,838,624. A 1 1/1998 Pilling et al. (US) 5,978,298 A 11/1999 Zheng 5.999,480 A 12/1999 Ong et al. 6,064,617 A 5, 2000 Ingall (*) Notice: Subject to any disclaimer, the term of this 6,130,834. A 10/2000 Mirkey et al. patent is extended or adjusted under 35 U.S.C. 154(b) by 614 days. * cited by examiner (21) Appl. No.: 10/372,196 Primary Examiner Thuan Do (74) Attorney, Agent, or Firm—Dickstein Shapiro LLP (22) Filed: Feb. 25, 2003 (57) ABSTRACT (65) Prior Publication Data An antifuse latch device and method for performing a US 2003/O131336A1 Jul. 10, 2003 redundancy pretest without the use of additional test cir O O cuitry is disclosed. Conventional antifuse latch devices are Related U.S. Application Data designed such that a redundancy pretest cannot be per (63) Continuation of application No. 09/640,741, filed on formed on the antifuse latch device once the antifuses are Aug. 18, 2000, now Pat. No. 6,553,556. programmed but rather requires additional circuitry to map the appropriate address bits to test the redundant row or (51) Int. Cl. column. The present invention adds a level translating G06F 7/50 (2006.01) inverter to a conventional antifuse latch device, thus allow (52) U.S. Cl. ............................... 71.6/4; 716/17: 703/14 ing the antifuse latch device to simulate an unblown antifuse (58) Field of Classification Search .................... 716/1 by isolating the antifuse from the latch. 716/2, 4, 17, 18; 703/14 See application file for complete search history. 18 Claims, 3 Drawing Sheets -195 204 202 U.S. Patent Dec. 5, 2006 Sheet 1 of 3 US 7,146,585 B2 S6 U.S. Patent Dec. 5, 2006 Sheet 2 of 3 US 7,146,585 B2 961)^ t . all - - - - - - - as - a s an - - - - - r U.S. Patent US 7,146,585 B2 ZO? OIH£º US 7,146,585 B2 1. 2 PROGRAMMABLE ELEMENT LATCH has an 8-bit binary address of 00100100, then the appropri CIRCUIT ate antifuses in a bank of 8 antifuses are blown to store this address. The individual antifuses are generally contained in CROSS REFERENCE TO RELATED antifuse latch devices which generate a digital value or APPLICATIONS signal indicating whether the antifuse is blown or unblown and may be arranged in groups of 8, each group of 8 defining The present application is a continuation application of the address fuses for one antifuse bank. U.S. patent application Ser. No. 09/640,741, filed on Aug. When an address in the memory device is accessed, a 18, 2000, now U.S. Pat. No. 6,553,556 the disclosure of compare circuit compares an incoming address to addresses which is herewith incorporated by reference in its entirety. 10 stored in the antifuse banks to determine whether the incom ing address matches an address containing a defective BACKGROUND OF THE INVENTION memory cell. If the compare circuit determines such a match, then it outputs a match signal to a row or column I. Field of the Invention decoder. In response, the row or column decoder causes an The present invention relates generally to a device and 15 method for testing semiconductor electrical devices. In appropriate redundant row or column to be accessed, and particular, the present invention relates to simulating a ignores the defective primary row or column in the array. programmable state of a device when the device has already After antifuses have been programmed to store an address been programmed to another programmable state. of a defective primary row or column, testing often occurs II. Description of the Related Art where it would be beneficial if the antifuse latch device In order to ensure proper operation, semiconductor could maintain a state other than that programmed. For devices are typically tested before being packaged into a example, an antifuse latch device may physically have a chip. A series of probes on a test station electrically contact blown antifuse, but need to simulate an unblown state to test pads on each die to access the semiconductor devices on the different configurations of the redundant rows or columns. die. For example, in a semiconductor memory device, the 25 Redundant elements are typically tested by assigning a probes contact address pads and data input/output pads to pretest address to each antifuse bank. This pretest address is access selected memory cells in the memory device. Typical hard coded so that each memory device has the same dynamic random access memory (“DRAM) devices redundant pretest address, and the test program is therefore include one or more arrays of memory cells arranged in rows valid for every device. Additional test circuitry is required and columns. Each array of memory cells includes word or 30 on the memory device to achieve this hard coding of the row lines that select memory cells along a selected row, and pretest addresses. As the number of redundant elements bit or column lines (or pairs of lines) that select individual increases, the amount of test circuitry required to define the memory cells along a row to read data from, or write data to, pretest addresses also increases. For ease of testing, it is the cells in the selected row. desirable to have the ability to test redundant elements using In a test procedure, predetermined data or Voltage values 35 pretest addresses even after the elements have been pro are typically written to selected row and column addresses grammed to repair defective memory elements, e.g. after a that correspond to certain memory cells, and then the Voltage repair address has been programmed into the antifuse bank. values are read from those memory cells to determine if the Traditionally, in a pretest test mode, the antifuse bank is read data matches the data written to those addresses. If the forced to output a match in response to a pretest address read data does not match the written data, then the memory 40 regardless of the state of the antifuse latches. The forced cells at the selected addresses likely contain defects and the match is accomplished through the use of test circuitry, semiconductor device fails the test. which bypasses the antifuse latch versus input address Many semiconductor devices, particularly memory compare circuitry, and therefore is not accurate in terms of devices, include redundant circuitry on the semiconductor address to match signal delay. In order to generate the match device that can be employed to compensate for certain 45 signal, addresses must be decoded and logically combined detected failures. As a result, by enabling Such redundant with the pretest test modesignal to determine when to force circuitry, the device need not be discarded even if it fails a the match. This pretest address decoder increases in size as particular test. For example, memory devices typically the number of redundant elements on a memory device employ redundant rows and columns of memory cells so that increases because more address combinations are required to if a memory cell in a column or row of the primary memory 50 provide enough unique pretest addresses. Providing sequen array is defective, then an entire row or column or partial tial pretest addresses require an even larger pretest address row or column of redundant memory cells can be substituted decoder since more address terms are required for each therefor, respectively. bank. For example, in the prior art, it has been sufficient to Substitution of one of the redundant rows or columns is use just one address term ANDed with the pretest signal to conventionally accomplished by blowing selected antifuses 55 decode a redundant element fuse bank. A0 high would in a bank of antifuse latch devices to select redundant rows enable bank 0, A1 high would enable bank 1, A2 high would or columns to replace defective primary rows or columns. enable bank 2, etc. To avoid enabling multiple fuse banks, Each bank represents a memory address. If a given primary only address 0, 2, 4, etc. would be valid using this meth row or column in the array contains a defective memory cell, odology, and the maximum number of unique fuse bank antifuses in the bank of antifuses are blown such that the 60 pretest addresses is limited to the number of address inputs bank of antifuses produces a binary output matching the to the device. Current memory devices may require 3 or 4 defective address. An antifuse is a capacitive device that address terms be ANDed together to generate the required may be blown by applying a relatively high Voltage across number of pretest addresses. Another drawback of this it which causes the dielectric layer in the antifuse to break method is that the tester requires a large memory space for down and form a conductive path. A blown antifuse will 65 the pretest addresses even though only a few of the addresses conduct current while an unblown antifuse will not conduct are actually valid. Thus, there exits a need for an antifuse current. For example, if the defective primary row or column latch that can be temporarily programmed for test purposes US 7,146,585 B2 3 4 to a state which is independent of the programmed State and DETAILED DESCRIPTION OF PREFERRED which can ideally be programmed into sequential pretest EMBODIMENTS address states.