Volume 2, No. 6, June 2011 Journal of Global RResearchesearch in Computer Science RESEARCH PAPER Available Online at www.jgrcs.info A VALIDATION OF SIM-A WITH OVPSIM Gajendra Kumar Ranka *1 , Dr. Manoj Kumar Jain 2 1Research Scholar, Department of Computer Science, MLSU University, Udaipur [email protected] 2Associate Professor, Department of Computer Science, MLSU University, Udaipur [email protected] Abstract: The design of modern embedded systems requires automated modelling tools for faster design and for the study of various design tradeoffs. Such tools put together constitute an integrated environment where the designer can write the high level design specifications in a language and use these tools for automatic generation of system specific tools. The major contribution of this paper lies in design and development of retargetable simulator and validation of the simulator with different simulators like OVPSim {Open Virtual Platform}. Proposed simulator measures cycle count for application executed on processor. This paper discusses the OVP Simulators, its working and the different customisations that are required to execute the benchmark application on this Simulator. Keywords: ASIP, Application Specific Instruction Processors, Retargetable Simulator, Embedded Systems, Processors, ASIP Simulators, Design Space Exploration, OVP Simulator . select a suitable architecture. Possibility of suitable INTRODUCTION architecture is explored and the best architecture is selected that satisfy the different characteristics like minimum Modern electronics are controlled by processors that must hardware cost, performance and power. meet strict constraints in terms of performance, cost, size and power consumption. In a competitive market place, Instruction Set Generation: performance and cost are critical in differentiating one Till this step we have identified application requirements product from another. In addition, low cost and superior and the suitable architecture. Based on this input instruction performance increases the likelihood of broad consumer sets are generated in terms of required micro operation. This acceptance of new electronic products. Size constraints limit instruction set is used during the further steps for code the amount of functionality that can be incorporated into synthesis and hardware synthesis. product design. Finally low power consumption is necessary for portable electronic equipment that is battery operated. Code Synthesis: Till this step, architecture template, instruction set, and An ASIP is a processor that is designed to efficiently application are identified. This step generates the code. execute the software for a specific application. Regardless of Generated code can be retargetable code generator or whether a newly designed ASIP or a pre-existing processor compiler generator. core is used, the selected processor should be well suited for the given application. Although incorporating a complete Hardware Synthesis: system on a single IC may improve performance, cost, and In this step the hardware is generated using the ASIP power consumption requirements, such a high level of architectural template and instruction set architecture using integration constraints the size of the system components. standard tools Steps in ASIP Synthesis Architecture Design Space Exploration Various methodologies have been reported to meet these requirements. All these have been studied and five steps are System on Chip designs has various goals and objectives. suggested for synthesis of ASIPs [1] Design space consists of a set of parameters. The main focus of designers lies on minimal cost and maximal performance, Application Analysis: low power, high reliability etc. Architecture under Application is normally written in High level language. consideration requires a range of good parameter to explore. Proper analysis of this application under consideration is done and the output of the information is stored in some These parameters may take up the different values. Some of suitable intermediate format. Sometimes SUIF can be used the parameter suggested can be functional unit of different as intermediate format. Analysis of the application is type, Storage units, interconnect resources, number of essential as it provides the essential requirement from the memory units etc. Further the parameters can also be application that can guide for hardware synthesis as well as extended to size of instruction cache and size of data cache. instruction set generation. This has been a very crucial step for ASIP design. Design Space exploration helps the SOC designers to make the Architectural Design Space Exploration: trade-offs between these goals and arrive at the "optimal" Output of the Application analysis step along with the range design. Designers explore changes to the architecture or the of architecture for Design Space Exploration is used to instruction-set of the processor-memory system. Designers © JGRCS 2010, All Rights Reserved 93 Gajendra Kumar Ranka et al, Journal of Global Research in Computer Science, Volume 2 Issue (6), June 2011, select a suitable architecture that satisfy the performance and ISA simulators are less descriptive than full system power constraint and having minimum hardware cost. simulators. Their objective is to model processor alone.ISA Architecture is defined using some suitable architecture simulators performs the various functionalities. description language (ADL). It simulate and debug machine instructions of a processor Techniques for Performance Estimation type that differs from the simulation host, it also emphasis Two major techniques have been used for performance on investigating how the various instructions (or a series of estimation. They are scheduler based and simulator based. instruction) affect the simulated processor. Hence modeling In Scheduler based approach, application is scheduled to of the full computer system is unnecessary and would generate the output like cycle count. Architectural impose additional delay and complexity. Example of this component is already identified at this stage. Target type of simulator includes SimpleScalar [14], WWT-II [15], processor architecture can be given in the form of and RSIM [16]. Over the past decade, a few interesting description file. ADLs have been introduced together with their supporting software tools. These ADL include MIMOLA, UDL/I, nML, In Simulator based approach, application under ISDL, CSDL, Maril, HMDES, TDL, LISA, RADL, consideration runs on a simulator. Depending upon the EXPRESSION and PRMDL. architecture selected in above steps, application is simulated to compute the performance. CHALLENGES IN ASIP DESIGN Processor Models are extensively used in system design The development of a processor is a complex task, involving process. The system design process starts with an several development phases, multiple design teams and application and its implementation. Then the model is tested different development languages. The key phase in for its performance and other aspects. In such a scenario an processor design is architecture specifications since it serves integrated environment is required for the designer where as the basis for all remaining design phases. Although several tools exist like simulator, assembler, compiler etc. Hardware Description Languages (HDLs) are designed for Rewriting the tools after each design change is a tedious job. architecture implementation, in a traditional design flow, Hence automatic generation of these tools is more desirable these languages are also often used for the initial according to the design changes. specification of the processor. In this design phase tasks, such as hardware/software partitioning, instruction-set and Existing Retargetable Simulators Approaches micro-architecture definition is performed. Based on the Retargetable functional simulator (Fsimg) [2] focus on tools architecture specification, both the hardware implementation that deal with the machine language of processors, like and development of software is triggered. Both tasks are assemblers, disassembler, instruction set simulator basically independent and therefore performed by different etc.Retargetable Function Simulator (Fsimg) was designed experts and design methodologies. using Sim-nML language which is primarily an extension of the nML [3] language for processor modeling. Fsimg takes Hardware designers use HDLs such as VHDL or Verilog, the specification of the processor in the intermediate while software designers mostly utilize the C/C++ representation [4] and an executable for the processor in programming language. In addition, the target processor ELF [5] format and generates a functional simulator (Fsim) needs to be integrated into the SoC and the application which in turn gives the functional behaviour of the processor software needs to be implemented. Communication between model for the given program. the design teams is obviously difficult because of the heterogeneous methodologies and languages. REALTED WORK Considering the traditional processor design flow, the strong dependencies between the design phases imply a Over the past several decades a considerable amount of unidirectional design flow and prevent even minor research has been performed in the area of computer optimizations. Due to the different development languages, architecture simulation. These simulators can be broadly changes to the architecture are difficult to communicate and divided into several categories: