SPARC T4™ Supplement to the Oracle SPARC Architecture 2011 Draft D0.4, 14 Feb 2012 Privilege Levels: Privileged and Nonprivileged Distribution: Public Part No.No: 950-5766-00 ReleaseRevision: 1.0, Draft 2002 D0.4, 14 Feb 2012 Oracle Corporation 4150 Network Circle Santa Clara, CA 95054 U.S.A. 650-960-1300 2 SPARC T4 Supplement • Draft D0.4, 14 Feb 2012 Copyright © 2011, Oracle and/or its affiliates. All rights reserved. Oracle and Java are registered trademarks of Oracle and/or its affiliates. Other names may be trademarks of their respective owners. AMD, Opteron, the AMD logo, and the AMD Opteron logo are trademarks or registered trademarks of Advanced Micro Devices. Intel and Intel Xeon are trademarks or registered trademarks of Intel Corporation. All SPARC trademarks are used under license and are trademarks or registered trademarks of SPARC International, Inc. UNIX is a registered trademark licensed through X/Open Company, Ltd. 4 SPARC T4 Supplement • Draft D0.4, 14 Feb 2012 Contents 1 SPARC T4 Basics . 1 1.1 Background . 1 1.2 SPARC T4 Overview . 2 1.3 SPARC T4 Components . 3 1.3.1 SPARC Physical Core . 3 1.3.2 L3 Cache. 5 2 Data Formats . 1 3 Registers . 1 3.1 Floating-Point State Register (FSR) . 1 3.2 Ancillary State Registers (ASRs) . 1 3.2.1 Tick Register (TICK) . 2 3.2.2 Program Counter (PC) . 2 3.2.3 Floating-Point Registers State Register (FPRS) . 3 3.2.4 General Status Register (GSR) . 3 3.2.5 Software Interrupt Register (SOFTINT). 3 3.2.6 System Tick Register (STICK) . 3 3.2.7 System Tick Compare Register (STICK_CMPR). 4 3.2.8 Compatibility Feature Register (CFR) . 5 3.2.9 Pause (PAUSE) . 7 3.3 Privileged PR State Registers . 7 3.3.1 Trap State Register (TSTATE) . 8 3.3.2 Processor State Register (PSTATE) . 8 3.3.3 Trap Level Register (TL). 9 3.3.4 Current Window Pointer (CWP) Register . 9 3.3.5 Global Level Register (GL) . 9 4 Instruction Formats . 1 5 Instruction Definitions . 1 5.1 Instruction Set Summary . 1 5.2 SPARC T4-Specific Instructions . 7 5.3 PREFETCH/PREFETCHA . 7 5.4 WRPAUSE . 8 5.5 Block Load and Store Instructions . 10 5.5.1 Block Initializing Store ASIs . 13 5.6 Integer Multiply-Add . 15 5.8 AES Operations (4 operand) . 17 5.9 AES Operations (3 operand) . 17 5.10 DES Operations (4 operand) . 17 5.11 DES Operations (2 operand) . 18 5.12 Camellia Operations (4 operand) . 18 5 5.13 Camellia Operations (3 Operand). 18 5.14 Hash Operations . 18 5.15 CRC32C Operation (3 operand) . 19 5.16 MPMUL . 19 5.17 MONTMUL . 19 5.18 MONTSQR . 19 6 Traps. 1 6.1 Trap Levels. 1 6.2 Trap Behavior . 1 7 Interrupt Handling . 1 7.1 CPU Interrupt Registers. 1 7.1.1 Interrupt Queue Registers . 1 8 Memory Models . 1 8.1 Supported Memory Models . 1 8.1.1 TSO . 2 8.1.2 RMO . 2 9 Address Spaces and ASIs . 1 9.1 Address Translation . 1 9.2 Address Spaces . 1 9.2.1 SPARC T4 supports a 52-bit virtual address space. 52-bit Virtual and Real Address Spaces 1 9.3 Alternate Address Spaces . 2 9.3.1 ASI_REAL, ASI_REAL_LITTLE, ASI_REAL_IO, and ASI_REAL_IO_LITTLE 8 9.3.2 ASI_SCRATCHPAD. 8 10 Performance Instrumentation . 1 10.1 SPARC Performance Instrumentation Counter. 1 11 Implementation Dependencies . 1 11.1 SPARC V9 General Information . 1 11.1.1 Level-2 Compliance (Impdep #1). 1 11.1.2 Unimplemented Opcodes, ASIs, and ILLTRAP . 1 11.1.3 Trap Levels (Impdep #37, 38, 39, 40, 114, 115) . 1 11.1.4 Trap Handling (Impdep #16, 32, 33, 35, 36, 44) . 1 11.1.5 Secure Software . 2 11.1.6 Address Masking (Impdep #125). 2 11.2 SPARC V9 Integer Operations. 2 11.2.1 Integer Register File and Window Control Registers (Impdep #2) 2 11.2.2 Clean Window Handling (Impdep #102) . 2 11.2.3 Integer Multiply and Divide. 2 11.2.4 MULScc . 3 11.3 SPARC V9 Floating-Point Operations . 3 11.3.1 Overflow, Underflow, and Inexact Traps (Impdep #3,.