Device and Circuit-level Models for Carbon Nanotube and Graphene Nanoribbon Transistors Michael Loong Peng Tan Queens’ College University of Cambridge A dissertation submitted for the degree of Doctor of Philosophy January 2011 Declaration This dissertation is the result of my own work and includes nothing which is the outcome of work done in collaboration except where specifically indicated in the text. This thesis has not been submitted in whole or in part as consideration for any other degree or qualification at the University of Cambridge or any other University or similar institution. In compliance with regulations, this thesis does not exceed 65,000 words, and contains 109 figures. Michael Loong Peng Tan January 2011 ii To my wonderful parents and sister, for their guidance, support, love and enthusiasm. I would not have made it this far without your motivation and dedication to my success. Thank you, Mama and Daddy, I love you both. iii Acknowledgement First of all, I am thankful to my supervisor, Prof. Gehan Amaratunga for his valuable insight, guidance, advice and time. I would like to take this opportunity to record my sincere gratitude for his supports and dedication throughout the years. My thankfulness also goes to Prof. Vijay K. Arora, my mentor from Wilkes University. His immense support and encouragement gave me the strength to go forward. I wish to express my heartfelt thanks to Prof. Razali Ismail for the advice and supports. I could not complete my study without the help and discussions with Chin Shin Liang, Desmond Chek, David Chuah and Caston Urayai. Their contributions in quantum physics and circuit simulation in the aspect of this dissertation are greatly appreciated. I would also like to acknowledge John Norcott for his computing assistance. Also, thank you to my friends namely Tee Boon Tuan, Chong Cheng Tung and Javier Wong and Lim Kian Min. I cherish the ideas they have given me, their supports and warmhearted friendships. I would also like to thank Malaysia Ministry of Higher Education and Universiti Teknologi Malaysia for the award of advanced study fellowship. On a personal note, I would like to thank my family who has always supported me and the encouragement they have given me. iv List of Publications Michael L. P. Tan and Gehan A. J. Amaratunga, “Performance Prediction of Gra- phene-Nanoribbon and Carbon Nanotube Transistor”, Eleventh International Con- ference on the Science and Application of Nanotubes, (NT10), 27 June – 2 July 2010, Montreal, Quebec, Canada. Michael L. P. Tan and Gehan A. J. Amaratunga, “Performance Prediction of Gra- phene-Nanoribbon and Carbon Nanotube Transistor”, Proceedings of the IEEE on International Conference on Enabling Science and Nanotechnology, (Nanotech Malaysia 2010), 1-3 December 2010, KLCC, Malaysia. v Abstract Device and Circuit-level Models for Carbon Nanotube and Graphene Nanoribbon Transistors Michael Loong Peng Tan Metal-oxide semiconductor field-effect transistor (MOSFET) scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. After forty years of advances in integrated circuit (IC) technology, the scaling of silicon (Si) MOSFET has entered the nanometer dimen- sion with the introduction of 90 nm high volume manufacturing in 2004. The latest technological advancement has led to a low power, high-density and high-speed gen- eration of processor. Nevertheless, the scaling of the Si MOSFET below 22 nm may soon meet its’ fundamental physical limitations. This threshold makes the possible use of novel devices and structures such as carbon nanotube field-effect transistors (CNTFETs) and graphene nanoribbon field-effect transistors (GNRFETs) for future nanoelectronics. The investigation explores the potential of these amazing carbon structures that exceed MOSFET capabilities in term of speed, scalability and power consumption. The research findings demonstrate the potential integration of carbon based technology into existing ICs. In particular, a simulation program with inte- grated circuit emphasis (SPICE) model for CNTFET and GNRFET in digital logic applications is presented. The device performance of these circuit models and their design layout are then compared to 45 nm and 90 nm MOSFET for benchmarking. It is revealed through the investigation that CNT and GNR channels can overcome the limitations imposed by Si channel length scaling and associated short channel effects while consuming smaller channel area at higher current density. vi Contents 1 Introduction 1.1 Background …………………………………………………………………. 1 1.2 Problem Statements …………………………..………………………….. 3 1.3 Objectives …………………………..………….…………………………. 4 1.4 Contributions …………………………..………….……..................... 4 1.5 Thesis Organization …………………………..…………................ 5 1.6 References …………………………..…………................................... 7 2 Overview of Carbon and Silicon-Based Technology 2.1 Carbon Nanotubes ………………………..………………………….. 8 2.1.1 Energy-Momentum Relation ……………………………… 12 2.1.2 Bandstructure of a Zigzag Nanotube …………….......... 13 2.1.3 Schottky Barrier CNTFET …………………………………. 14 2.1.4 Synthesis …………………………………………………………… 17 2.2 Graphene ……………………………………………………………………. 18 2.2.1 Synthesis …………………………………………………………… 22 2.3 Carbon-based Nanoelectronics ……………………….................... 23 2.4 Current Transport Models ………............................................. 24 2.5 Device Modeling ……………..……………………..……………..……. 28 2.6 Conclusion ……………..……………..…………….……………………... 33 2.7 References ……………..……………..…………….……………………... 35 vii Contents 3 Device Model 3.1 Introduction …………..……………..……………...…………………….. 44 3.2 Modeling Approaches ………..……………...………………………….. 45 3.3 Low Dimensional Structure Modeling ………………………………. 46 3.4 Electrostatic Capacitance ………………………………………………. 54 3.5 Quantum Capacitance …………………………………………………… 55 3.6 Channel, Quantum and Contact Resistance …………………… 57 3.7 Source and Drain Resistance ………………………………………. 59 3.8 Energy Dispersion in GNR and CNT ………………………….. 60 3.9 Model Verification ………………………………………………………… 63 3.10 MATLAB Implementation ……………………………………………. 66 3.11 Analog Behavior Modeling in PSPICE ………………...……….. 69 3.12 Comparison with MOSFET model ………..………..………........... 73 3.13 RC and Propagation Delay ………..………..………...................... 75 3.14 Conclusion ..………..………..……..……………….…..……..………….. 82 3.15 References ..………..………..……..……….…..……..………………….. 83 4 Performance Prediction of the CNTFET and the GNRFET 4.1 Introduction ………..……..………..………………………………………. 87 4.2 Performance Metric ………..……..………..…………………………….. 88 4.3 Performance Benchmarking ………..……..………..…………………. 94 4.4 Conclusion ………..……..………..………..……….…………………. 108 4.5 References ………..…..………..………..……….………..................... 110 5 Layout and Circuit Analysis 5.1 Introduction ……..………..……..………..………..………................ 111 5.2 Generic 45 nm PDK ………..……..………..………..………………. 112 5.2.1 MOSFET Layout for CNTFET Benchmarking ………. 113 5.2.2 MOSFET Layout for GNRFET Benchmarking ………. 115 viii Contents 5.3 Generic 90 nm PDK ……………………………………………………. 117 5.3.1 MOSFET Layout for CNTFET Benchmarking ………. 118 5.3.2 MOSFET Layout for GNRFET Benchmarking ………. 120 5.4 Digital Logic Circuit for CNTFET and GNRFET …………….. 122 5.5 Conclusion ………..……..………..………..……….………................ 138 5.6 References ………..…..………..…………………………………………. 139 6 Conclusions and Future Work 6.1 Summary ……..…..………..………..…………..……………………….. 140 6.2 Future Work ……..…..………..………..…………..……….…………… 142 6.3 References ……..…..………..………..…………..…………….……… 145 Appendix A Research Methodology A.1 Introduction ……………..……………..…………………………….…… 147 A.2 Electrical Modeling ……………..……………..…………………………. 148 A.2.1 MATLAB ……………..……………..………………………….. 150 A.2.2 HSPICE ……………..……………..………………………….. 151 A.2.3 PSPICE ……………..……………..………………………….. 153 A.2.4 CADENCE ……………..……………..………………………….. 154 A.3 Conclusion ……………..……………..…………………………….…… 157 A.4 References ……………..……………..…………………………….…… 158 Appendix B Low Dimensional Modeling B.1 Quasi-Two Dimensional Model ………….…………………………… 161 B.1.1 Density of States for Q2D Structure ………….………….. 161 B.1.2 Electron Concentration for Q2D Structure …………….. 161 B.1.3 Instrinsic Velocity for Q2D Structure ………….……….. 162 ix Contents B.2 Quasi-One Dimensional Model ………….……………………………. 163 B.2.1 Density of States for Q1D Structure ………….………….. 163 B.2.2 Electron Concentration for Q1D Structure ………….…. 164 B.2.3 Instrinsic Velocity for Q1D Structure ………….………… 165 B.3 Summary of Relative Formulas ………….…………………………… 166 B.4 Gamma Function ………….……………….…………………………….. 167 x List of Abbreviations ABM - Analog Behaviour Model ALD - Atomic Layer Deposition AMS - Analog Mixed Signal BSIM - Berkeley Short-Channel IGFET Model CAD - Computer Aided Design CDF - Component Description Format CMC - Compact Modeling Council CMOS - Complementary Metal-Oxide-Semiconductor CNTFET - Carbon Nanotube Field-Effect Transistor DC - Direct Current DG - Double Gate DIBL - Drain-Induced Barrier Lowering DOS - Density of States DRC - Design Rules Check ECAD - Electronic Computer-Aided Design EDA - Electronic Design Automation EDP - Energy Delay Product FDSOI - Fully-Depleted Silicon on Insulator FET - Field Effect Transistor GaAr - Galium Arsenide GCA - Gradual Channel Approximation GDSII - Graphic Database System II GHz - Giga Hertz xi GNR - Graphene Nanoribbon Field-Effect Transistor GUI - Graphical User Interface IBM - International Business Machines IC - Integrated Circuit IGFET - Insulated Gate Field-Effect Transistor InP - Indium Phosphide LVS - Layout versus Schematic MFP - Mean Free Path MMSIM