Logic Synthesis Techniques for High-Speed Circuits David Baneres˜ Advisors: Jordi Cortadella (UPC) Mike Kishinevsky (Intel Corporation) Disertation submitted in partial fulfillment of the requirements for the Degree of Doctor in Philosophy in Computer Science Departament de Llenguatges i Sistemes Informatics` (LSI) Universitat Politecnica` de Catalunya January 3, 2008 Acknowledgments This thesis would not have been possible without the perseverance and guidance of my thesis advisors, Jordi Cortadella and Mike Kishinevsky. Jordi with his continuous support, encouragement, supervision and constructive criticism made him a reliable reference in the most critical moments of my research. Mike showed me the real world inside the computer aided design. I would also thank him for his comments, advice and patience during my internship in Intel Corporation. I must also acknowledge my colleagues Robert Clariso, Kyller Costa, Federico Heras, Nilesh Modi, Albert Oliveras, Enric Rodriguez at the LSI Department for making the stay especially en- joyable. This work has been partially funded by a grant from Intel Corporation; a scholarship (FI) from Generalitat de Catalunya; and the projects CICYT TIC2001 2476 (MAVERISH), and CICYT TIN2004 07925 (GRAMMARS). Finally, thanks to my beloved Maria Elena, for sharing this experience with me, and helping me in making it possible through the difficult times, and to my parents for their love, caring, and understanding. Abstract Complexity in the design of electronic systems is significantly increasing in DSM technologies. Synthesis requires more powerful techniques to meet the specification constraints and capable to run in affordable time in the larger designs. One of the phases in VLSI design is logic synthesis. This thesis introduces several methods in this phase to meet one of the primary objectives in circuit design: timing optimization. Several contributions are presented. First, a solver of Boolean relations has been developed. A Boolean relation is able to capture more flexibility than conventional approaches based on don’t cares. This work received the best paper award in the Design Automation Conference (DAC’04). The second contribution is a new partitioning algorithm based on the concept of vertex domina- tor. When optimization algorithms are applied on these clusters, this partition offers more possibil- ities for restructuring towards delay minimization compared to other techniques based on min-cut. A multi-level decomposition approach is also defined using the solver of Boolean relations: a time-driven n-way decomposition. Functions are decomposed to improve the performance (speed) using a small library of multi-input gates. Finally, an integrated approach for layout-aware interconnect optimization is presented. This technique combines gate duplication and buffer insertion in the same framework with incremental placement. Similar to the principle of the Engineering Change Order (ECO), the circuit is incre- mentally improved by performing small modifications using fanout optimization techniques on top of the current placement. The contributions of the thesis have been published in the following papers: • D. Baneres, J. Cortadella, and M. Kishinevsky. A recursive paradigm to solve boolean rela- tions. In Proc. ACM/IEEE Design Automation Conference, pages 416–421, June 2004 • D. Baneres, J. Cortadella, and M. Kishinevsky. Dominator-based partitioning for delay opti- mization. In ACM Great Lakes Symposium on VLSI, pages 67–72, 2006 • D. Baneres, J. Cortadella, and M. Kishinevsky. Layout-aware gate duplication and buffer insertion. In Proc. Design, Automation and Test in Europe (DATE), pages 1367–1372, 2007 • D. Baneres, J. Cortadella, and M. Kishinevsky. A recursive paradigm to solve boolean rela- tions. In IEEE Transactions on Computers, 2007 (Submitted) Contents 1 Introduction 1 1.1 Design flow . 2 1.1.1 Classical design flow . 2 1.1.2 DSM design flow . 4 1.2 Motivation and contributions . 5 1.3 Organization of this document . 7 2 State of the art 9 2.1 Overview on Logic Synthesis . 9 2.1.1 Terminology . 10 2.1.2 Two-level Minimization . 11 2.1.3 Multi-Level Logic Synthesis . 13 2.1.4 Flexibility in Boolean functions . 16 2.1.5 BDD-based optimization . 19 2.2 Decomposition . 21 2.3 Partitioning . 22 2.4 Technology-dependent techniques . 23 2.4.1 Technology mapping . 24 2.4.2 Gate Sizing . 25 2.4.3 Buffer insertion . 25 2.4.4 Gate duplication . 26 2.4.5 Physical-aware logic synthesis . 26 3 A Recursive Paradigm To Solve Boolean Relations 27 3.1 Introduction . 27 3.2 Overview . 28 3.3 Previous work . 30 3.4 Preliminaries . 31 i ii CONTENTS 3.5 Basics of Solving a Boolean relation . 34 3.5.1 Semi-lattice of well-defined Boolean relations . 34 3.5.2 Projection of a Boolean relation to a Multiple-output ISF . 35 3.5.3 Solution of a Multiple-output ISF . 37 3.5.4 Divide-and-conquer . 38 3.6 Details of the Boolean relation solver . 40 3.6.1 Characteristic functions . 41 3.6.2 Quick solver . 41 3.6.3 The recursive approach . 42 3.7 Further implementation details . 46 3.7.1 Representation of relations . 46 3.7.2 Exploration of solutions . 46 3.7.3 Cost function . 46 3.7.4 Split strategy . 47 3.7.5 Minimization of ISFs . 47 3.7.6 Symmetries in Boolean Relations . 48 3.8 Solving Boolean equations . 50 3.9 Efficiency of the method . 53 3.9.1 Comparison with the expand-reduce-irredundant paradigm . 53 3.9.2 Experimental results . 54 3.10 Application of Boolean relations . 55 3.10.1 Logic decomposition . 55 3.10.2 Experimental results . 57 3.11 Conclusions . 58 4 Dominator-based Partitioning for Logic Synthesis 61 4.1 Introduction . 61 4.2 Previous work . 62 4.3 Overview . 67 4.4 Preliminaries . 69 4.4.1 Vertex Dominator . 69 4.4.2 Windows . 70 4.5 Partition Method . 71 4.5.1 Core of the algorithm . 71 4.5.2 Example of a partitioning . 74 4.5.3 Preserving topological order . 76 4.6 Timing-driven optimization . 77 4.7 Experimental results . 79 CONTENTS iii 4.7.1 Configuration of the algorithms . 80 4.7.2 Comparison with DEPART and speed up . 80 4.7.3 Comparison with hMetis . 82 4.7.4 Trade-off between area and delay . 83 4.8 Conclusions . 84 5 Window-based timing-driven n-way decomposition 87 5.1 Introduction . 87 5.2 Previous work . 88 5.3 Overview . 91 5.4 Background . 93 5.5 Recursive n-way decomposition . 94 5.6 Implementation aspects . 97 5.6.1 BREL solver . 97 5.6.2 BREL cost functions . 97 5.6.3 Look-up table . 99 5.7 Experimental results . 100 5.7.1 Comparison with bi-decomposition . 100 5.7.2 Window-based n-way decomposition . 102 5.8 Conclusions . 103 6 Layout-Aware Gate Duplication and Buffer Insertion 105 6.1 Introduction . 105 6.2 Previous work . 106 6.2.1 Elmore delay model . 106 6.2.2 Buffer Insertion . 107 6.2.3 Gate duplication . 112 6.3 Overview . 112 6.4 Algorithm for interconnect optimization . 114 6.5 Algorithm for gate duplication . 115 6.5.1 Delay-oriented duplication . 116 6.5.2 Discussion . ..