AN ABSTRACT OF THE DISSERTATION OF Eric Kwesi Donkoh for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on June 13, 2013. Title: Design and Modeling of Low-Power Register File Memories Abstract approved: _______________________________________ Patrick Y. Chiang With the evolving popularity of new computing platforms such as Ultrabooks, Tablets, and Smart Phones, and the shift to multi-core computing, power is now the key performance limiter, a departure from the traditional frequency limitation. As such, increasingly low-power design solutions feature prominently in early architectural and design space exploration in CPU/SoC design. On a high performance CPU, majority of these early studies involve memories, especially Register Files. Register Files (RF) are the preferred memory element for fast data access and are therefore ubiquitous in modern microprocessor design, contributing approximately 30% of Intel’s 32nm CPU core power. The goal of this research is two-fold. First, it explores low-power design techniques to reduce RF leakage and dynamic power at minimal delay and area cost. We analyze RF power distribution, data residencies, signal activities, and logic dependencies in modern 32nm/22nm high performance microprocessors. We then propose new circuit techniques to reduce power in critical memory logic blocks such as the bitcell, write data distribution, read access data path, and decoder. We use innovative transistor stack-forcing techniques to reduce RF read bitline and decoder leakage by as much as 90% and delay by 30% at minimal to no area overhead compared to existing stacking approaches. An essential component of low-power design is an accurate predictive model (power, area, and timing) for early architectural and design space tradeoff analysis. On a high performance CPU, greater than 75% of RFs are custom designed due to design complexities and constraints (power, area, timing, low-voltage operation requirements). Existing models are particularly unsuited for custom RF because these models typically assume a generic RF circuit implementation and are therefore inaccurate for predicting unique RF topologies without requiring new model development. Furthermore, these models do not accurately address common design optimizations such as device sizing, data gating, segmentation, and device stacking that significantly impact the power profile of an RF. In the second part of this research we’ve developed a customizable predictive model that addresses these key limitations. The proposed model is a hybrid of empirical reference data and analytical equations. We use an empirical reference implementation data of a topology under study to capture topology- specific characteristics and analytically model the impact of cross-topology features such as changes in bit- width, entry-count, ports, and common circuit-level design optimizations such as segmentation, gating, device stacking, and sizing. We show how the proposed model can be customized for different RF topologies and other memory structures such as SRAM and ROM using the same model equations. We also demonstrate how the new predictive model, with <10% error, is used in the real world tradeoff analysis in the design of state-of-the-art high performance CPUs and SoCs. ©Copyright by Eric Kwesi Donkoh June 13, 2013 All Rights Reserved DESIGN AND MODELING OF LOW-POWER REGISTER FILE MEMORIES by Eric Kwesi Donkoh A DISSERTATION submitted to Oregon State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy Presented June 13, 2013 Commencement June 2014 Doctor of Philosophy Dissertation of Eric Kwesi Donkoh presented on June 13, 2013 APPROVED: Major Professor, representing Electrical and Computer Engineering Director of the School of Electrical Engineering and Computer Science Dean of the Graduate School I understand that my dissertation will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my dissertation to any reader upon request. Eric Kwesi Donkoh, Author ACKNOWLEDGEMENTS I will like to express my appreciation to Prof. Patrick Chiang for his flexibility towards the selection of research topic and his guidance towards this work. I would also like to express my gratitude to my committee members, Shih-Lien Lu, Bibiche Geuskens, Prof. Arun Natarajan, and Prof Abi Farsoni for expending their valuable time in guiding my PhD program. Great thanks to my co-workers Alicia Lower, Teck-Siong Ong, Yan Nee Too, Emily Shriver, and Ee Wah Lim for their support and contribution to various aspects of this research. An appreciation to co-worker Ataur Patwary for sharing his valuable OSU experience. I would also like to thank Nanda Siddaiah and Kurt Kreitzer for their support of this work. My sincerely thanks to the EECS graduate coordinators Nicole Thompson and Ferne Simendinger for their invaluable assistance in navigating the PhD process. Finally, a big thanks to all those who directly or indirectly impacted this work. This Dissertation is dedicated to Family and Friends No One Has A Monopoly On Ideas – Be Innovative!!! TABLE OF CONTENTS 1 INTRODUCTION ....................................................................................................................................... 1 1.1 Computing Trend ......................................................................................................................... 1 1.2 New Computing Platforms ChallengeS .................................................................................. 3 1.3 Memory Power .............................................................................................................................. 4 1.4 CPU Power Breakdown .............................................................................................................. 5 1.5 Reaserach Goal .............................................................................................................................. 6 1.5.1 Register File Low Power Design ................................................................................................................... 6 1.5.2 Array Power Modeling ..................................................................................................................................... 9 1.6 Research Methodology .............................................................................................................. 11 1.7 Dissertation Overview ............................................................................................................... 12 1.8 Related Publications ................................................................................................................... 12 1.9 Reference ....................................................................................................................................... 13 2 BACKGROUND – POWER OVERVIEW ....................................................................................... 15 2.1 CMOS Transistor Overview .................................................................................................... 15 2.1.1 Transistor Operation....................................................................................................................................... 15 2.1.2 The threshold voltage ..................................................................................................................................... 16 2.1.3 Transistor Operation in Super-threshold .................................................................................................. 19 2.1.4 Transistor Operation in Sub-Threshold .................................................................................................... 21 2.2 Leakage Sources .......................................................................................................................... 23 2.3 Ion and Ioff Tradeoff ................................................................................................................ 25 2.4 Logic and Functional Power Dissipation ............................................................................. 26 2.4.1 Leakage Power .................................................................................................................................................. 26 2.4.2 Dynamic Power ................................................................................................................................................ 32 2.4.3 Static Power ....................................................................................................................................................... 36 2.5 References ..................................................................................................................................... 37 3 BACKGROUND – REGISTER FILE MEMORIES ...................................................................... 38 3.1 Memory Element ........................................................................................................................ 38 3.2 Register File Architectural Overview ..................................................................................... 39 3.3 Register Files Design .................................................................................................................. 40 3.3.1 Register File Organization ............................................................................................................................