82078 44 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER Y Small Footprint and Low Height Y Integrated Tape Drive Support Package Ð Standard 1 Mbps/500 Kbps/ 250 Kbps Tape Drives Y Enhanced Power Management Ð Application Software Transparency Y Perpendicular Recording Support for Ð Programmable Powerdown 4 MB Drives Command Y Integrated Host/Disk Interface Drivers Ð Save and Restore Commands for Zero-Volt Powerdown Y Fully Decoded Drive Select and Motor Ð Auto Powerdown and Wakeup Signals Modes Y Programmable Write Precompensation Ð Two External Power Management Delays Pins Ð Consumes No Power While in Y Addresses 256 Tracks Directly, Powerdown Supports Unlimited Tracks Y 16 Byte FIFO Y Integrated Analog Data Separator Ð 250 Kbps Y Single-Chip Floppy Disk Controller Ð 300 Kbps Solution for Portables and Desktops Ð 500 Kbps Ð 100% PC/AT* Compatible Ð 1 Mbps Ð Fully Compatible with Intel386TM SL Ð Integrated Drive and Data Bus Y Programmable Internal Oscillator Buffers Y Floppy Drive Support Features Ð Drive Specification Command Y Separate 5.0V and 3.3V Versions of the Ð Selectable Boot Drive 44 Pin part are Available Ð Standard IBM and ISO Format Y Available in a 44 Pin QFP Package Features Ð Format with Write Command for High Performance in Mass Floppy Duplication The 82078, a 24 MHz crystal, a resistor package, and a device chip select implements a complete solution. All programmable options default to 82078 compatible values. The dual PLL data separator has better perform- ance than most board level/discrete PLL implementations. The FIFO allows better system performance in multi-master (e.g., Microchannel, EISA). The 82078 maintains complete software compatibility with the 82077SL/82077AA/8272A floppy disk control- lers. It contains programmable power management features while integrating all of the logic required for floppy disk control. The power management features are transparent to any application software. The 82078 is fabricated with Intel's advanced CHMOS III technology and is also available in a 64-lead QFP package. *Other brands and names are the property of their respective owners. *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT © INTEL CORPORATION, 1996 December 1995 Order Number: 290474-003 82078 44 Pin CHMOS Single-Chip Floppy Disk Controller CONTENTS PAGE CONTENTS PAGE 1.0 INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 4.0 POWER MANAGEMENT FEATURES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 17 2.0 MICROPROCESSOR INTERFACE ÀÀÀÀÀ 9 4.1 Power Management Scheme ÀÀÀÀÀÀÀ 17 2.1 Status, Data, and Control 4.2 Oscillator Power Management ÀÀÀÀÀÀ 17 Registers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 4.3 Part Power Management ÀÀÀÀÀÀÀÀÀÀÀ 18 2.1.1 Status Register B (SRB, EREG EN e 1) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 9 4.3.1 Direct Powerdown ÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 2.1.2 Digital Output Register 4.3.2 Auto Powerdown ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 (DOR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10 4.3.3 Wake Up Modes ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 2.1.3 Enhanced Tape Drive 4.3.3.1 Wake Up from DSR Register (TDR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11 Powerdown ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 2.1.4 Datarate Select Register 4.3.3.2 Wake Up from Auto (DSR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11 Powerdown ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 18 2.1.5 Main Status Register 4.4 Register Behavior ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19 (MSR) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13 4.5 Pin Behavior ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 19 2.1.6 FIFO (DATA) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13 4.5.1 System Interface Pins ÀÀÀÀÀÀÀÀÀ 19 2.1.7 Digital Input Register (DIR) ÀÀÀÀÀ 14 4.5.2 FDD Interface Pins ÀÀÀÀÀÀÀÀÀÀÀÀ 20 2.2 Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 2.2.1 Reset Pin (``HARDWARE'') 5.0 CONTROLLER PHASES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 5.1 Command Phase ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20 2.2.2 DOR Reset vs DSR Reset 5.2 Execution Phase ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 (``SOFTWARE'' RESET) ÀÀÀÀÀÀÀÀÀÀ 14 5.2.1 Non-DMA Mode, Transfers 2.3 DMA Transfers ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 from the FIFO to the Host ÀÀÀÀÀÀÀÀÀ 21 3.0 DRIVE INTERFACE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 5.2.2 Non-DMA Mode, Transfers from the Host to the FIFO ÀÀÀÀÀÀÀÀÀ 21 3.1 Cable Interface ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14 5.2.3 DMA Mode, Transfers from 3.2 Host and FDD Interface Drivers ÀÀÀÀÀ 15 the FIFO to the Host ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 3.3 Data Separator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 15 5.2.4 DMA Mode, Transfers from 3.3.1 Jitter Tolerance ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 the Host to the FIFO ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 21 3.3.2 Locktime (tLOCK) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 5.2.5 Data Transfer Termination ÀÀÀÀÀ 22 3.3.3 Capture Range ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 5.3 Result Phase ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 3.4 Write Precompensation ÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 2 CONTENTS PAGE CONTENTS PAGE 6.0 COMMAND SET/DESCRIPTIONS ÀÀÀÀ 22 7.0 STATUS REGISTER ENCODING ÀÀÀÀÀ 46 6.1 Data Transfer Commands ÀÀÀÀÀÀÀÀÀÀ 34 7.1 Status Register 0 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 46 6.1.1 Read Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 34 7.2 Status Register 1 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 46 6.1.2 Read Deleted Data ÀÀÀÀÀÀÀÀÀÀÀÀ 35 7.3 Status Register 2 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 47 6.1.3 Read Track ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 35 7.4 Status Register 3 ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 47 6.1.4 Write Data ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36 8.0 COMPATIBILITY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 6.1.5 Write Deleted Data ÀÀÀÀÀÀÀÀÀÀÀÀ 36 8.1 Compatibility with the FIFO ÀÀÀÀÀÀÀÀÀ 48 6.1.6 Verify ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36 8.2 Drive Polling ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 6.1.7 Format Track ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37 6.1.7.1 Format Fields ÀÀÀÀÀÀÀÀÀÀÀÀÀ 38 9.0 PROGRAMMING GUIDELINES ÀÀÀÀÀÀÀ 48 6.2 Scan Commands ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 38 9.1 Command and Result Phase Handshaking ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49 6.3 Control Commands ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39 9.2 Initialization ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 49 6.3.1 Read ID ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39 9.3 Recalibrates and Seeks ÀÀÀÀÀÀÀÀÀÀÀÀ 51 6.3.2 Recalibrate ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39 9.4 Read/Write Data Operations ÀÀÀÀÀÀÀ 51 6.3.3 Drive Specification Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39 9.5 Formatting ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 53 6.3.4 Seek ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 9.6 Save and Restore ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 54 6.3.5 Sense Interrupt Status ÀÀÀÀÀÀÀÀÀ 40 9.7 Verifies ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55 6.3.6 Sense Drive Status ÀÀÀÀÀÀÀÀÀÀÀÀ 41 9.8 Powerdown State and Recovery ÀÀÀÀ 55 6.3.7 Specify ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 9.8.1 Oscillator Power Management ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 55 6.3.8 Configure ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 9.8.2 Part Power Management ÀÀÀÀÀÀÀ 55 6.3.9 Version ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42 9.8.2.1 Powerdown Modes ÀÀÀÀÀÀÀ 55 6.3.10 Relative Seek ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 42 9.8.2.2 Wake Up Modes ÀÀÀÀÀÀÀÀÀÀ 56 6.3.11 DUMPREG ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43 6.3.12 Perpendicular Mode 10.0 DESIGN APPLICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀ 56 Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43 10.1 Operating the 82078-3 in a 3.3V 6.3.12.1 About Perpendicular Design ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 56 Recording Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43 10.2 Selectable Boot Drive ÀÀÀÀÀÀÀÀÀÀÀÀÀ 58 6.3.12.2 The Perpendicular 10.3 How to Disable the Native Floppy Mode Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 43 Contoller on the Motherboard ÀÀÀÀÀÀÀÀ 59 6.3.13 Powerdown Mode 10.4 Replacing the 82077SL with a Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44 82078 in a 5.0V Design ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 59 6.3.14 Part ID Command ÀÀÀÀÀÀÀÀÀÀÀÀ 44 11.0 D.C. SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 62 6.3.15 Option Command ÀÀÀÀÀÀÀÀÀÀÀÀ 44 11.1 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀ 62 6.3.16 Save Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44 11.2 D.C. Characteristics ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 62 6.3.17 Restore Command ÀÀÀÀÀÀÀÀÀÀÀ 44 11.3 Oscillator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 63 6.3.18 Format and Write Command ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45 12.0 A.C. SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 64 6.3.19 Lock ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 45 12.1 Package Outline for the 44-Pin QFP Part ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 70 13.0 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 71 3 82078 44 PIN 290474±1 Figure 1-0. 82078 44 Pin Pinout Table 1.0. 82078 (44 Pin) Description @ H/W Symbol Pin Ý I/O Description Reset HOST INTERFACE RESET 34 I N/A RESET: A high level places the 82078 in a known idle state. All registers are cleared except those set by the Specify command. A0 40 I N/A ADDRESS: Selects one of the host interface registers: A1 39 A2 A1 A0 Access Register A2 38 0 0 0 R Reserved 0 0 1 R/W Status Register B SRB 0 1 0 R/W Digital Output Register DOR 0 1 1 R/W Tape Drive Register TDR 1 0 0 R Main Status Register MSR 1 0 0 W Data Rate Select Register DSR 1 0 1 R/W Data Register (FIFO) FIFO 1 1 0 Reserved 1 1 1 R Digital Input Register DIR 1 1 1 W Configuration Control Register CCR CSÝ 41 I N/A CHIP SELECT: Decodes the base address range and qualifies RDÝ and WRÝ. RDÝ 42 I N/A READ: Read control signal for data transfers from the floppy drive to the system. 4 82078 44 PIN Table 1.0 82078 (44 Pin) Description (Continued) @ H/W Symbol Pin Ý I/O Description Reset HOST INTERFACE (Continued) WRÝ 43 I N/A WRITE: Write control signal for data transfers to the floppy drive from the system. DRQ 44 O DMA REQUEST: Requests service from a DMA controller. Normally active high, but will go to high impedance in AT and Model 30 modes when the appropriate bit is set in the DOR. DACKÝ 1 I N/A DMA ACKNOWLEDGE: Control input that qualifies the RDÝ, WRÝ inputs in DMA cycles. Normally active low, but is disabled in AT and Model 30 modes when the appropriate bit is set in the DOR.