Efficient Memoryless Cordic for FFT Computation Mario Garrido, J. Grajal Conference Publication N.B.: When citing this work, cite the original article. ©2016 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Original Publication: Mario Garrido , Efficient Memoryless Cordic for FFT Computation, Efficient Memoryless Cordic for FFT Computation, 2007. (), pp.II-113-II-116. http://dx.doi.org/10.1109/ICASSP.2007.366185 Copyright: www.ieee.org Postprint available at: Linköping University Electronic Press http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70360 EFFICIENT MEMORYLESS CORDIC FOR FFT COMPUTATION M. Garrido and J.Grajal Departamento de Seales, Sistemas y Radiocomunicaciones ETSIT, Universidad Politecnica´ de Madrid Ciudad Universitaria s/n, 28040, Madrid, Spain [email protected] ABSTRACT The main contributions of our implementation are the follow- A new memoryless CORDIC algorithm for the FFT com- ing: putation is proposed in this paper. This approach calculates ² The rotator requires no memory, so the area hardly de- the direction of the micro-rotations from the control counter pends on the number of rotations which permits the cal- of the FFT, so the area of the rotator hardly depends on the culation of FFTs of a high number of points. number of rotations, which is particularly suitable for the com- ² The circuit fulfills real time requirements due to a high putation of FFTs of a high number of points. Moreover, the speed, a low latency and a throughput of one sample new CORDIC presents other advantages such as the simpli- per clock cycle. fication of the basic CORDIC processor used to calculate the micro-rotations, or an easy way to compensate the intrinsic ² The basic CORDIC processor, which computes the mi- gain of the CORDIC algorithm. Additionally, the VLSI im- cro-rotations, has been simplified based on a novel mo- plementation of the algorithm is a pipeline architecture with dification of the rotation sequence. high performance in terms of speed, throughput and latency. ² The intrinsic scale of the conventional CORDIC has Index Terms— Memoryless systems, Pipeline process- been reduced and an easy compensation is proposed. ing, Discrete Fourier transforms, Very-large-scale integration. ² The implementation is highly parametrizable, which ma- kes it adaptable to any application. 1. INTRODUCTION Important work has been carried out on the implementa- tion of the FFT rotators but, to the best of our knowledge, no Nowadays, signal processing systems are characterized by a previous work presents a memoryless scheme like the one we high complexity and real time operation. To satisfy these re- propose here. In some cases the memory size has been re- quirements of real time operation, FPGA-based hardware ac- duced, but the reduction is only to log2N [2], or 0:5N [3], celeration systems provide a reasonable speedup with very where N is the number of points of the FFT. Additionally, low cost. The enormous integration density of nowadays tech- other important aspects of the CORDIC rotators that can be nologies has allowed current FPGAs to hold a complete sys- found in the literature are the design of the basic CORDIC tem in a single chip, the so-called System on Chip (SoC) ap- processor [2, 4, 5], the scale factor of the CORDIC [2, 5], the proach. In this context, any improvement in speed or area of computation of the rotation vector [6], or the performance in a particular implementation drastically improves the perfor- terms of speed [4, 7] and latency [6]. All these points have mance and scope of the whole signal processing system. also been addressed in this work. The FFT is a key element in most signal processing ap- plications. When analyzing its structure, we can see that it presents important demands of memory, both for the rotations 2. CORDIC ALGORITM and samples. Given that the multiplication carried out to per- form rotations in the FFT requires very large area, most ar- The CORDIC algorithm [1] decomposes the desired rotation chitectures use the CORDIC algorithm [1] instead of conven- angle, θ, into a sum of a set of M predefined angles, ®i, with tional multipliers. i = 0;:::;M ¡ 1: In this work we propose an efficient architecture for the CORDIC algorithm that allows very large FFT implementa- MX¡1 tions without a significant increase in area. Moreover, the θ = ®i + ² (1) proposed architecture improves the performance of previous i=0 approaches, what results in a very efficient implementation. where ² is the error of the approximation, and, 3.1. Angle generator ¡1 ¡i ®i = §tg (2 ) (2) According to the Cooley-Tukey algorithm [8], an N-point FFT Thus, the rotation is accomplished iteratively according can be divided into n = logrN stages where r is the radix of to: ¡i the FFT. We will assume that both N and r are a power of 2. xi+1 = xi ¡ yi±i2 ¡i (3) In this context, the angle sequence at the stage s 2 f1 : : : ng yi+1 = yi + xi±i2 has a length L = rs and is repeated N=rs times in order to where ±i indicates the direction of the so called micro-rotation. perform the N required rotations. In a conventional CORDIC, ±i 2 f¡1; 1g. It means that The angle sequence, depends on the chosen radix. Thus, all the rotations are accomplished, what leads to a constant the following sequence must be generated for radix 2: gain of the rotator. This intrinsic gain can be compensated by multiplying the output by: a = 0; 0; 0; 0;:::; 0; 1; 2; 3;::: (5) s | {z } | {z } MY¡1 MY¡1 2s¡1 2s¡1 ¡1 ¡i K = cos(®i) = cos(tg (2 )) (4) and, for radix 4, i=0 i=0 3. MEMORYLESS CORDIC ARCHITECTURE a = 0; 0; 0; 0;:::; 0; 1; 2; 3;:::; 0; 2; 4; 6;:::; 0; 3; 6; 9;::: s | {z } | {z } | {z } | {z } 4s¡1 4s¡1 4s¡1 4s¡1 Figure 1 shows the architecture of the designed CORDIC. The (6) main difference between this circuit and other CORDIC rota- Generalizing for any value of radix, the angle sequence tors is the fact that no memory is required. Thus, the rota- will be generated by concatenating r subsequences: tion sequence is obtained from the counter used to control the whole N-point FFT, which counts from 0 to N ¡ 1. Firstly, s¡1 the rotation angle, θ, is calculated and then the corresponding 0; p; 2p; : : : ; (r ¡ 1)p (7) rotation sequence is generated. As occurs in a conventional where p = 0; 1; 2; : : : ; r ¡ 1. CORDIC, ±i 2 f¡1; 1g, leading to a constant gain. Finally, Figure 2 shows how these sequences can be obtained from the sequence is adapted to the module that rotates the signal the 0 to N ¡1 counter of an N-point FFT. According to (7), p in order to simplify the design. is the value of the log2r most significant bits of the counter at each stage, and the rest of the bits counts from 0 to (rs¡1 ¡1). Fig. 1. CORDIC Rotator. The micro-rotations are calculated by means of a pipeline, where each stage rotates the input data a certain angle, ac- cording to the CORDIC algorithm. The number of stages (a) Radix 2 (b) Radix 4 can be selected by the user depending on the desired preci- sion. Besides, it must be noted that the rotation of 45± is not considered. In a conventional CORDIC rotator the 45± rota- Fig. 2. Angle generation tion places the remainder angle in the range [¡45±; 45±]. By contrast, in our design this is achieved by the 180± and 90± In order to normalize all the sequences of the stages of the rotations, which introduces no error and reduces the intrinsic FFT to the minimum rotation angle, θmin(rad) = 2¼=N the s gain of the CORDIC. On the other hand, due to the pipeline values of the sequences must be multiplied by q = N=r or, structure of the micro-rotations, the circuit works at a rate of equivalently, shifted log2(q) bits: 1 sample per clock cycle. Finally, the output data can be scaled in order to compen- m = q ¢ a = 0; 0; 0; 0;:::; 0; q; 2q; 3q; : : : (8) s s | {z } | {z } sate the intrinsic gain of the CORDIC rotator. 2s¡1 2s¡1 The sequence ms represents the rotation angle if the cir- adequate the design to a certain application, the number of cumference is divided into N identical angles, i.e., if θ 2 micro-rotation stages, the bits used in the calculations of the [0;:::;N ¡ 1] is one of the angles of the sequence, rotation vector and the selection of the first angle where the approximation is considered are parameters of the circuit. 2¼ θ(rad) = ¡ θ (9) N 3.3. Micro-rotations and rotation adapter The explained method is used to generate the angles of both DIT (Decimation In Time) and DIF (Decimation In Fre- The 180± and 90± rotations previous to the CORDIC stages quency) decompositions, considering that s = 1 is the input are easily calculated by interchanging the vector components stage in the DIT case and the output stage in a DIF FFT. and/or changing their sign. On the other hand, the CORDIC rotations are accomplished by the following circuit: 3.2. Generation of the rotation vector Given the rotation angle, θ, the rotation generator calculates the vector ± that controls the micro-rotations.