CSC414 I/O Bus Architecture Computer Internal Bus Common pathway for data to travel System Technologies Processor bus (on-chip bus) Fundamentals - Connects units within CPU to on-chip cache Cache bus (back-side bus) - Connects CPU to L1, L2, L3 Caches Memory bus (front-side bus) Digital Forensics Center - Connects main memory and processor Department of Computer Science and Statics THINK BIG WE DO Backplane bus (system bus) U R I - Connects I/O to the CPU and memory http://www.forensics.cs.uri.edu - Connects all peripheral cards and connectors I/O Bus Architecture I/O Bus Architecture Consists of an I/O device, I/O device User Program Parallel Bus 0000011000001000 controller, system bus, and a device driver Operating System - All bits are sent at the same time Device I/O Manager - 8-bit, 16-bit, 32-bit, 64-bit buses - Any hardware that can provide input to or accept Software Device Driver - Limited length output from the CPU - Timing and synchronization issues at high Device Controller System Bus speeds because of variability in line quality - Hardware that connects directly to the device I/O Bus - Internal Buses are normally parallel - Controls (commands the device) Device Controller Serial Bus Bus - Transfers data to/from device - Bits are sent sequentially - Interacts with CPU Hardware Device - Must send more bits per second to Device Driver equal speed of parallel bus - Software that controls the I/O devices - Can send bits at higher speeds Device Controller 0 ISA and EISA Microchannel ISA (Industry Standard Architecture) Bus MCA (Microchannel Architecture) Bus - Older ISA Bus - 8 bit data path - Designed for IBM PS/2 computers - Newer ISA Bus - 16 bit data bus - 32 bit data transfer path (4 bytes) - will accept both 8 and 16 bit expansion cards - Automatic Card Configuration - 8 MHz clock rate for data transfers - 10 MHz Clockrate EISA (Extended Industry Standard) Bus - 4MB/s transfer - 32 bit data transfer path (4 bytes) - Will not accept 8 or 16 bit ISA expansion cards - Data transfer rate (33Mb/s) - Not common (proprietary) - About 4MB/s - Will accept 8 and 16 bit ISA cards VESA PCI VESA Local Bus (VL-Bus) PCI Local Bus - Video Electronics Standards Association - Peripheral Component Interconnect - 32 bit data transfer rate - 32-bit or 64-bit data path - 25MHz to 50MHz clock speed - Developed by Intel in early 1992 - Common on Intel 486 motherboards - Model for Intel’s Plug and Play (PnP) - Designed by NEC in 1992 to resolve video problems in Windows - PCI cards do not have jumpers and switches they are configured through - Can move data 32 bits at a time enabling transfer between the CPU and video or hard drive at full 32 bit data width of 486 chip software PCI Bus Speeds - Drawback - limit of two boards per local bus. - PCI expansion slots will not support ISA cards 133 MB/s (32-bit at 33 MHz) - Increasing the number of local busses decreases performance 266 MB/s (32-bit at 66 MHz slightly - PCI has become the standard (64-bit at 33 MHz) 533 MB/s (64-bit at 66 MHz) AGP PCI Express Accelerated Graphics Port (AGP) Bus PCI-Express Bus - PCI local bus became a bottleneck - Serial Bus - Advanced graphics adapter developed by Intel in - High speed bus so small variation in time can 1997 is the intended replacement skew parallel transmissions - AGP is a bus specification that enables 3D graphics to display on personal computers AGP main memory use is dynamic - Controller has VRAM 2 Gbits/sec to 128 Gbits/sec PCI Express slots - When not used for accelerated graphics, (from top to bottom: x4, x16, x1 and x16) 250 MB/sec to 16 GB/sec - main memory is restored for use by the operating Traditional 32-bit PCI slot (bottom) system or applications up to 2133 MB/sec (2 GB/sec) PCI PCI Express Internal Bus CPU Technologies Memory AGP Digital Forensics Center Department of Computer Science and Statics THINK BIG WE DO IDE/ATA U R I http://www.forensics.cs.uri.edu.