The Development of Sub-25 nm III-V High Electron Mobility Transistors A THESIS SUBMITTED TO THE DEPARTMENT OF ELECTRONICS AND ELECTRICAL ENGINEERING FACULTY OF ENGINEERING UNIVERSITY OF GLASGOW IN FULFILMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY By Steven Bentley July 2009 c Steven Bentley 2009 All Rights Reserved \Le bon Dieu est dans le d´etail." Gustave Flaubert \Der Teufel steckt im Detail." Blixa Bargeld Abstract High Electron Mobility Transistors (HEMTs) are crucially important devices in mi- crowave circuit applications. As the technology has matured, new applications have arisen, particularly at millimetre-wave and sub-millimetre wave frequencies. There now exists great demand for low-visibility, security and medical imaging in addition to telecom- munications applications operating at frequencies well above 100 GHz. These new applications have driven demand for high frequency, low noise device opera- tion; key areas in which HEMTs excel. As a consequence, there is growing incentive to explore the ultimate performance available from such devices. As with all FETs, the key to HEMT performance optimisation is the reduction of gate length, whilst optimally scaling the rest of the device and minimising parasitic extrinsic influences on device performance. Although HEMTs have been under development for many years, key performance metrics have latterly slowed in their evolution, largely due to the difficulty of fabricating devices at increasingly nanometric gate lengths and maintaining satisfactory scaling and device performance. At Glasgow, the world-leading 50 nm HEMT process developed in 2003 had not since been improved in the intervening five years. This work describes the fabrication of sub-25 nm HEMTs in a robust and repeatable manner by the use of advanced processing techniques: in particular, electron beam litho- graphy and reactive ion etching. This thesis describes firstly the development of robust gate lithography for sub-25 nm patterning, and its incorporation into a complete device process flow. Secondly, processes and techniques for the optimisation of the complete device are described. This work has led to the successful fabrication of functional 22 nm HEMTs and the de- velopment of 10 nm scale gate pattern transfer: simultaneously some of the shortest gate length devices reported and amongst the smallest scale structures ever lithographically defined on III-V substrates. The first successful fabrication of implant-isolated planar high-indium HEMTs is also reported amongst other novel secondary processes. i Acknowledgements I am indebted to many people for their input on this work, without whom it would never have been completed. I would like to thank Iain Thayne for his unique mentoring input, and for striking a great balance as supervisor between allowing me freedom and providing guidance when required. He also provided many curries. All the members of the Ultrafast Systems Group both past and present deserve thanks for their transfer of knowledge and sharing in the many delights of fabrication. Particular thanks are due to Dave Moran and Richard Hill for their effective concoction of cama- raderie, wisdom and sarcasm (1:1:1), and for so many thought-provoking discussions. I am indebted to Xu Li for developing the dry etch processes used in this work, and for his apparently telepathic control over SF6 etch times, and to Helen McLelland and Su- san Ferguson for their support and optimistic understanding. Kevin Docherty is to be praised for his encyclopaedic familiarity with the wiles of the VB6 and for his essential guidance on alignment techniques. Thanks are also due to Billy Smith and Colin How for their skills in TEM sample preparation and imaging. The entire staff of the James Watt Nanofabrication Centre deserves thanks for the smooth running of the facilities, which is a testament to their dedication and hard work. Heartfelt thanks are also due to my family and friends, who have supported me through my studies, and whose unwavering belief and patience have enabled me to remain largely sane. My mother deserves a medal for her many hours of treating physics as a foreign language whilst proof-reading, which have transformed this thesis into something much less unintelligible. Undertaking this work has been made possible by the constant love and encouragement of Vicki Allan, who has seen the incoherent, obsessive-compulsive side and decided to marry me anyway. Finally, to all those friends and colleagues who are too many to name, but who have made such a huge difference, untold thanks are due. The combined humour, kind words, prayers and wisdom have transformed this work from a worthwhile academic pursuit to an enjoyable life experience. Many thanks. ii Contents 1 Associated Publications 1 2 Introduction 2 3 The High Electron Mobility Transistor 5 3.1 Introduction . 5 3.2 Device overview . 6 3.3 Electron transport in semiconductors . 7 3.3.1 Drift, diffusion, scattering and mobility . 8 3.3.2 Field-dependent transport . 12 3.4 Heterostructures . 14 3.4.1 Modulation doping and 2-Dimensional Electron Gas . 18 3.5 Semiconductor interfaces and surfaces. 20 3.5.1 Metal-semiconductor interfaces. 21 3.5.2 Electron transport across barriers . 23 3.5.3 Rectifying (Schottky) contacts . 26 3.5.4 Ohmic contacts . 27 3.6 Device operation . 28 3.6.1 Long-channel electron transport . 30 3.6.2 Gate voltage modulation and I-V characteristics . 33 3.7 Device elements and the small-signal equivalent circuit . 39 3.7.1 Parasitic elements and effects on performance . 41 3.7.2 High frequency performance and figures of merit. 46 3.8 Scaling the HEMT . 51 3.8.1 Gate capacitances and resistance . 51 iii 3.8.2 Non-equilibrium electron transport . 53 3.8.3 Effective channel length . 61 3.8.4 Vertical scaling . 62 3.8.5 Limits to scaling . 64 3.9 Summary . 64 4 Fabrication techniques 66 4.1 Introduction . 66 4.2 Epitaxial material growth . 66 4.2.1 Molecular beam epitaxy . 67 4.3 Lithography . 69 4.3.1 Optical lithography . 70 4.3.2 Electron beam lithography . 72 4.4 Pattern transfer . 82 4.4.1 Additive and subtractive processes . 83 4.5 Material deposition and removal . 84 4.5.1 Wet etching . 84 4.5.2 Plasma processing . 86 4.5.3 Dielectric plasma deposition . 91 4.5.4 Metallisation . 93 4.6 Generic HEMT process flow . 95 4.6.1 Marker/ohmics . 95 4.6.2 Isolation. 97 4.6.3 Gates . 97 4.6.4 RF Bondpads . 98 4.7 Self-aligned process flow . 99 4.8 Summary . 100 5 Characterisation and metrology 101 5.1 Introduction . 101 5.2 Material characterisation and the van der Pauw technique . 101 5.3 Contact resistances and the Transmission Line Method . 105 iv 5.4 Device characterisation . 109 5.4.1 D.C. measurements . 110 5.4.2 R.f. measurements . 111 5.4.3 Calibration . 113 5.4.4 S-parameter de-embedding . 113 5.4.5 Extraction of figures of merit . 116 5.5 Summary . 117 6 Literature Review 119 6.1 Gate lithography . 119 6.2 Materials Advances . 123 6.2.1 Development of Metamorphic Growth Technology . 125 6.2.2 Optimisation of the Recess Region . 127 6.2.3 Alternative Channel Materials and Designs . 128 6.3 Optimising Device Parasitics . 129 6.4 HEMTs in digital applications. 131 6.5 Performance simulation . 132 6.6 Summary . 132 7 Development of sub-25 nm HEMT processes 134 7.1 Introduction . 134 7.2 Single-step gate processes at Glasgow . 134 7.3 Fundamental lithographic limitations . 135 7.3.1 Bi-lithography strategies . 140 7.3.2 Other limitations of single-step processes. 141 7.4 Development of a two-step gate methodology . 143 7.4.1 Selection of gate resist . 145 7.4.2 Silicon nitride processing . 147 7.4.3 Upper gate lithography. 155 7.4.4 Alignment . 156 7.4.5 Complete gates and resistance measurements . 158 7.5 Integrated device process flow . 162 7.5.1 Resist uniformity and sample topography . 163 v 7.6 Initial material design . 166 7.6.1 Non-annealed layer design . 168 7.6.2 C216 and C217 material characterisation. 175 7.7 First-generation 22 nm device results and discussion . 176 7.7.1 Discussion . 183 7.8 Second-generation C216 devices : gate length variation . 186 7.9 InAlAs surface processing . 191 7.9.1 Silicon nitride overetch . 192 7.9.2 Post-recessing surface treatments . 194 7.10 Third-generation device results : gate length variation . 200 7.10.1 Discussion . 208 7.11 Summary . 213 8 Device Development 216 8.1 Introduction . 216 8.2 Alignment techniques . 216 8.3 10 nm gate process development . 218 8.3.1 High resolution technique . 220 8.3.2 Length reduction technique . 224 8.3.3 Discussion . 227 8.4 Ohmic contact development. 227 8.4.1 Issues around the fabrication of short ohmic gaps . 230 8.4.2 Thin metal recipes . 231 8.4.3 Gap lithography . 232 8.5 Material design. 235 8.6 Device fabrication . 244 8.7 Summary . 250 9 Implant Isolation 252 9.1 The motivation for implant isolation . 252 9.2 Theory . 253 9.3 Experimental Design and Sample Preparation . 255 vi 9.4 Measurements and Results . 259 9.4.1 Non-annealed TLM Measurements . 260 9.4.2 Non-annealed van der Pauw Measurements . 261 9.4.3 Iron Implant Annealing Studies . 262 9.4.4 RF Loss Measurements . 264 9.4.5 Transmission Line Measurements . 265 9.4.6 Implanted device fabrication. 267 9.5 Implantation intermixing effects . 270 9.6 Summary . 275 10 Conclusions and Future Work 277 A Device Process Flows 282 A.1 22 nm Devices - Large source-drain gaps .