Schnftinrtiht Informatik^ Proceedings of the Second Workshop on Hierarchical Test Generation Microelectronics Technology Park, Duisburg, Germany September 25-26, 1995 (organized by: W. Geisselhardt & H.-D. Hummer) Universität Duisburg Bericht Nr. Sl-15 September 1995 Nachdruck: März 1996 ISSN: 0942-4164 fHerausßeßer. Gerhard-Mercator-Universltät-GH Duisburg Institut für Informatik D-47048 Duisburg Tel.: (+203) 3789-211. 379-2006/ 2008 e-mail: [email protected] UNIVERSITÄTSBIBLIOTHEK HANNOVER TECHNISCHE UB/TIB Hannover 89 INFORMATiONSBSBLIOTHEK 115 134 964 Proceedings of the 2nd Workshop on Hierarchical Test Generation Contents Keynote R. Segers, Philips | Session 1 Design Validation H.-D. Huemmer, H. Toepfer; Gerhard Mercator University Duisburg (Germany) Automated Teslcase Selection for Simulation Based VHDL Design Verification Matthias Gulbins, Bernd Sträube; Fraunhofer Ges. IIS/EAS Dresden (Germany) 16 Improving High-Level Design Validation by L/sing Debug Mode | Session 2 Hierarchical Testpattern Generation Methodology \ R. Ubar; Technical University of Tallinn (Estonia) 18 Hierarchical Test Generation Based on Alternative Graph Model K. Tilly, A. Pataricza, B. Sallay; Technical University Budapest (Hungary) 19 High Level Functional Test Generation Based on Constraint Satisfaction Methods and Heuristic Cost Functions B. Emshoff, M. Kaibel, W. Geisselhardt; Gerhard Mercator University Duisburg (Germany) 20 Structural ATPG using Functional Information | Session 3 Hierarchical Testpattern Generation Methodology II Wencheng Li, James R. Armstrong; Virginia Tech Blacksburg (U.S.A.) 29 Behavioral Test Generation with Fault Coverage Enhancement Juraj Stefanovic, Elena Gramatova; Slovak Technical University Bratislava (Slovakia) 30 RTL Level Test Generation Using Genelic Algorilhm and Simulated Annealing U. Gläser, H.T. Vierhaus; GMD (Germany), 31 F. Corno, P. Prinetto, M. Sonza Reorda; Politecnico diTorino (Italy) Efficient Communication in Mixed-Level Hierarchical Test Pattern Generation Eva Fordran, Bernd Sträube, Jens Schönherr; Fraunhofer Ges. IIS/EAS Dresden (Germany) 34 Hierarchical Test Pattern Generation Algorithmfor Multiple Stuck-at Faults in Combinational Circuits Keynote R. Niederhagen, Synopsys 37 [ Session 4 High Level Fault Modeling and Simulation Milan Duda, Jana Bezakova, Elena Gramatova; 39 Slovak Acad. of Science Bratislava (Slovakia) Fault Simulation Algorithm on Behavioral Level from VHDL Circuit Descripüon Containing Several Process A. Rucinski, B. Dziurla-Rucinska, R. Harisson; U. New Hampshire (U.S.A), 40 S.K. Tewksbury; West Virginia U. (U.S.A.), P. Bisgambiglia, J.F. Santucci; U. de Corse (France) Analysis of physical failures in Space Applications using a High Level Fault modeling Scheme Martin Keim, Bernd Becker; Albert-Ludwigs-University, Freiburg im Breisgau,Germany 42 Rolf Krieger; Joh. Wolfg. Goethe-University, Frankfurt, Germany Hybrid Fault Simulation for Hierarchical Sequential Circuits Session 5 Special Aspects of Testgeneration and Simulation Ulrich Bieker; University of Dortmund (Germany) 47 RESTART: A Retargetuble Compiler for Self-Test Programs Based on Constraint Logic Programming A. Hunger, S. Werner; Gerhard Mercator University Duisburg (Germany) 49 Modelling Hierarchy for the Purallelization of the Testgeneration for Digital Circuits Session 6 Design for Testability Sergey L. Frenkel; Russian Academy of Sciences, Moscow (Russia) 51 Behavioral Testability Characteristics for Hierarchical Test Generation Volker Schoeber; University of Hannover (Germany) 54 A DFT Expert System for Integrated Circuits F. Corno, P. Prinetto, M. Sonza Reorda; Politecnico di Torino (Italy) 55 Design for Testabilitx and Design for Synthesizability: an Industrial Approach T. Wiemers , W. Splettstoesser; Siemens Corp. (Germany), 56 H.-D. Huemmer , W. Geisselhardt; Gerhard Mercator Univ Duisburg (Germany) Smart Testlogic - A New Approach to Module Level Test -5-.