A DIGITALLY PROGRAMMABLE CURRENT SCHMITT-TRIGGER W. PRODANOV AND M. C. SCHNEIDER Laboratório de Circuitos Integrados Universidade Federal de Santa Catarina (UFSC) Cx Postal 476 – Campus – CEP 88040-900 Florianópolis – SC – Brasil – email: [email protected] Abstract Vx This work presents a new compact structure for a digitally programmable current Schmitt-trigger comparator, which is compatible with VLSI processes Iin and allows low-voltage operation. The digital - Iref + Iref programmability is achieved by means of MOSFET-only current dividers. The effects of offset voltages and limited frequency response of opamps’s on the accuracy (1a) Tranfer function of the comparator are shown. Vdd Vdd Vdd IDIFF M3 1.Introduction M1 _ VX + The development of basic circuit cells is very important VM3 VY to decrease the development time of more complex IREF N1 A1 Vss systems. Comparators can be seen as a class of these A2 N3 cells. IIN N2 M2 Schmitt-triggers are often used because of its property of IREF V eliminating the comparator chatter. Current Schmitt- Y Vbias VX Vbias Vss triggers are particularly useful in photo detectors, optic Vss Vss remote control and medical instruments [1]. (1b) Electrical scheme This work presents a new compact structure for a digitally programmable current Schmitt-trigger Fig. 1: Non-programmable Schmitt-trigger. comparator, which is compatible with VLSI processes. The circuit that generates V is a simple series Several different current comparators structures have BIAS association of two identical transistors as shown in Fig. 2 already been presented [2-5]. Some of them operate at [8-10]. high speed [2, 3], others present high accuracy or are offset-free [2, 4, 5], but none of them have the digital VDD programming characteristic. Combined with self- adaptive structures, this comparator can achieve high IREF speed and high accuracy. MA This paper is organized as follows. Section 2 presents the VDD basic non-programmable structure of the Schmitt-trigger VBIAS comparator. In section 3, we show how to program the MB Schmitt-trigger by means of MOSFET-only current V dividers. In section 4, we analyze the effects of offset SS voltages and frequency response of opamp’s on the Fig. 2 – Circuit to generate the bias voltage VBIAS. accuracy of the comparator. Simulation results are Transistor M3 was designed to operate in the triode shown in section 5. region for an input current below 1.5×IREF. Indeed, M3 acts an I-to-V converter. 2. The basic structure of the comparator Now, we can start to analyze the operation of the The basic non-programmable structure of the proposed comparator. The comparator (A2) output changes Schmitt-trigger can be seen in Fig. 1. whenever the current IDIFF equals zero, as can be seen in The bias voltage VBIAS is such that it allows maximum Fig. 1. Under this condition, voltage VM3 is zero, too, current swing through M3. It also guarantees the drain and the voltages on the non-inverter and inverter inputs currents ID_M1 and ID_M2, through M1 and M2 of A2 opamp are the same and equal to VBIAS, driving respectively, to have the same magnitude, equal to IREF the comparator to the threshold state. [6,8]. Thus: The current IDIFF is given by (2) and (3), depending on ID_M1 = ID_M2 = IREF (1) the state of VX. IDIFF = IIN + IREF, if VX = HIGH (2) shows a single 2-bit network. The terminal labeled VC IDIFF = IIN – IREF, if VX = LOW (3) can be used as an ‘ON/OFF’ switch. The voltage at ‘sum’ and ‘dump’ terminals must be the same. As If V is on the “high” state, M1 is ‘ON’ and M2 ‘OFF’. X previously mentioned, ‘a’ and ‘b’ are controlled by According to (2), to have I = 0, I must be equal to DIFF IN binary words applied to the MOS switches in the parallel ‘–I ’. In the same way, when V is “low” M2 is ‘ON’ REF X branches of the MOCD. Equation (4) gives ‘a’ and ‘b’, and M1 is ‘OFF’. According to (3), to have I = 0, I DIFF IN where ‘b’ is the digital word in base 10 and ‘n’ is the must be ‘+I ’. Hence, we obtain a hysteresis loop with REF number of bits. the transition points at ‘±IREF’. b+1 a,b= (4) 3. Programmable structure 2n One can program the Schmitt-trigger if current dividers substitute for transistors M1 and M2 in the circuit shown The operational amplifiers of the comparator are Class A in Fig. 1. These dividers present an input current equal to Miller opamp’s. The main characteristics of the Miller opamp’s are shown in Table I. In order to improve the ‘I ’ and output currents equal to ‘a×I ’ and ‘(1- REF REF comparator performance, each differential amplifier a)×I ’, where ‘a’ is digitally controlled by a binary REF should have a specific design. A1 should have a very word. Fig 4 illustrates the new hysteresis loop, together high GBW and A2, which operates as a voltage with the programmable circuit. Note that ‘a’ and ‘b’ are comparator, must be as fast as possible. programmed by a digital word. Vx DC gain 97 dB Gain-Bandwidth 2.0 MHz Product (GBW) Iin Phase Margin 64 Degree Maximum Output -b Iref a Iref 96 mA Current Supply Current 144 mA (4a) Tranfer function Slew Rate 2.3 V/ms PMOS input pair Vdd VX IREF Table I – Characteristics of the Miller opamp M3 · b0 IDIFF (1-b) IREF · · b _ n + V M3 VY 4. Error analysis I b IREF One can find two main errors in the hysteresis curve: a IN N1 A1 A2 Vss N3 right or left shift from the origin and an opening of the N2 a IREF V hysteresis loop, as depicted in Fig. 6. The first one is BIAS caused by an offset current that adds a systematic error · b0 VX · VBIAS (1-a) I · REF VBIAS bn to the comparison level for any ‘a’ or ‘b’. Its main error Vss sources are the offset voltages of the opamp’s. The V IREF Vss Y second effect is caused by a switching delay between the (4b) Electrical scheme instants that IIN reaches the comparison level and the Fig. 4 – Digitally programmable Schmitt-trigger actual VX switching. The phase delay of opamp A1 and the transient response of A2 are responsible for this V C VDD switching delay, as will be shown in section 4.2. IN 1 2 IIN VX VX Ideal Ideal Shifted Opened b0 b0 b1 b1 (1 - a) IIN IIN / IREF IIN / IREF Dump -Line a IIN (6a) Shifted loop (6b) Opened loop Sum-Line Fig. 5 – 2-bit MOCD Fig. 6 –Graphical representation of the main errors in the hysteresis loop The current divider is a well-known and widely applied network called Mosfet-Only-Current-Divider (MOCD). 4.1 Hysteresis loop shift This current divider was introduced in [11] and it The offset voltages of both A1 and A2 contribute to the operates similarly to the classic R-2R network. Its shift of the hysteresis loop. First let us consider only the principle of operation is detailed in [11, 12]. Fig. 5 effect of offset voltage ‘VOS_1’ of A1. It is easy to see this offset voltage gives rise to an offset current equal to æfö f (8) qc=arctgç÷@ VOS_1×gms3 through M3, where gms3 is given by èGBWøGBW 'WæVDD-VT ö (5) gms3=mnCOXç-VBIAS÷ Now, we are going to consider the effect of this phase Lèn ø delay on the comparator threshold. Let ‘qc’ be the phase On the other hand, assuming the offset voltage of A2 to between v0 and iin, at a specific frequency. The ideal be ‘VOS_2’, the switching of VX occurs at an input switching occurs when IIN reaches aIREF (bIREF). At this voltage of A2 equal to VBIAS+VOS_2. Therefore, an extra point, V0 is supposed to be equal to VBIAS. However, V0 current equal to VOS_2×gms3 through M3 is needed to will equal VBIAS a “little bit late” due to the phase delay compensate VOS_2. The combination of the two offset ‘qc’. The delay is graphically shown in Fig. 8. voltages results in an offset current in the hysteresis loop IIN given by I = (V + V )×gms . OFF OS_1 OS_2 3 X ×I This error can be minimized with a very careful layout to i REF Actual switching minimize VOS. Smaller gms3 values would reduce IOFF. Di However, A1 would saturate for smaller values of IIN. a×IREF Consequently, the value of gms3 would have to be Ideal increased. switching t 4.2 Opening of the hysteresis loop qs As mentioned before, the opening of the loop is caused by a switching delay. The two main sources of this error are the finite gain-bandwidth product of A1 and the transient response of comparator A2. The limited frequency response of A1 needs a careful attention V0 because its effect is more difficult to eliminate. To verify t the influence of the frequency response of A1, let us consider Fig. 7, which represents a first order AC equivalent of the circuit in Fig. 4. To simplify the VBIAS analysis, the conversion iin to v0 is assumed to be linear. Furthermore, the effect of the conductances of the qc MOCD’s in the frequency range that we are interested in Fig. 8 – Error Di caused by qc is very small owing to the high opamp DC gain. The relative error ‘Di/aIREF’ is given by (9), where Xi is gms3 peak value of IIN normalized to IREF.