Stanford University EE 218: Introduction to Nanotechnology and Nanoelectronics H.-S. Philip Wong Professor of Electrical Engineering Stanford University, Stanford, California, U.S.A. [email protected] http://www.stanford.edu/~hspwong Center for Integrated Systems EE 218 Department of Electrical Engineering Stanford University What is Nanotechnology? Source: Apple Computer, Inc. 2 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University The Beginning of Nano Source: IBM Source: IBM Invention of the Scanning Tunneling Gerd Binnig, Heinrich Rohrer Microscope (STM) Nobel Prize, 1986 3 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: IBM 4 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 5 H.-S. Philip Wong EE 218 Department of Electrical Engineering The Scale of Things -- Nanometers and More Source: NSF website Things NaturalNanotechnology ProgressGeneratingNewExcitement Things Manmade 10-2 m 1 cm Source: J. Sphorer (IBM) 10 mm Head of a pin 21st Century 1-2 mm Challenge 1,000,000 nanometers = Ant 10-3 m 1 millimeter (mm) ~ 5 mm MicroElectroMechanical Devices Dust mite 10 -100 µm wide 0.1 mm 200 µm 10-4 m 100 µm Fly ash Human hair ~ 10-20 µm ~ 10-50 µm wide O P 10-5 m 0.01 mm O O 10 µm O OOO O OOOOOO O The Microworld The O O O O O O O O Red blood cells S S S S S S S S with white cell ~ 2-5 µm 1,000 nanometers = 10-6 m 1 micrometer (µm) Red blood cells Pollen grain Visible spectrum Combine nanoscale 10-7 m 0.1 µm building blocks to make 100 nm functional devices, e.g., a photosynthetic reaction center with integral semiconductor storage 0.01 µm 10-8 m Nanotube electrode 10 nm Nanotube transistor ~10 nm diameter Nanoworld The ATP synthase 10-9 m 1 nanometer (nm) DNA 6 ~2-1/2 nm diameter 10-10 m 0.1 nm Quantum corral of 48 iron atoms on copper surface Carbon nanotube Atoms of silicon positioned one at a time with an STM tip ~2 nm diameter spacing ~tenths of nm Corral diameter 14 nm Stanford University US Nanotechnology Funding Source: M. Roco, NNI (10/29/2003). 7 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University NNI Funding by Agency Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 8 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Global Nanotechnology Investment Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 9 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 10 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco, NNI (10/29/2003). 11 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco (NNI), National Research Council, Washington, D.C., March 23, 2005 12 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: M. Roco (NNI), National Research Council, Washington, D.C., June 27, 2005. 13 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University http://www.research.ibm.com/pics/nanotech/ 14 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Questions? 15 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University An 8 nm Transistor Gate Gate Source Drain Lgate=8 nm Source: IBM 16 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Atoms are starting to look big Source: IBM When one atom high “bumps” look significant in a photo of your transistors, both their manufacture and behavior are “exciting” 17 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Integrated Circuit Complexity Source: G. Moore, Intel (2003) 18 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: K. David (Intel) 19 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Source: K. David (Intel) 20 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University State-of-the-Art Technology 90 nm technology 65 nm technology Source: M. Bohr, Intel (2004) 21 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University A view from Intel 22 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Time Horizon Blue Sky 2004 2007 2010 2013 2016 2020 Physical Gate 37 nm 25 nm 18 nm 13 nm 9 nm 6 nm Ultrathin SOI High k gate dielectric Double-Gate CMOS FinFET Strained Si, Ge, SiGe raised source/drain Strained Si, Ge, SiGe top-gate doped channel channel Gate halo buried oxide buried oxide channel depletion layer back-gate isolation isolation isolation Silicon Substrate Source Drain Silicon Substrate buried oxide Evolutionary Revolutionary 23 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Poly-silicon Future Si Devices Tox=16A Gate Tsi=7 nm Source H. Shang et al., IEDM 2002 Gate Drain Source NiSi Gate NiSi Drain B. Doris et al., IEDM 2002 Si Tox = 1.6nm J. Kedzierski et al., IEDM Fin 2001 , IEDM 2002 T = 25nm si K. Rim et al., IEDM 2003 Si BOX CoSi on W 2 RSD Strained silicon HfO2 60nm SiO2 SiGe Si Buried oxide M. Yang et al., IEDM 2003 B. Lee et al., IEDM 2002 24 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Innovation Overtakes Scaling in Driving Performance Innovation (invention) will increasingly dominate performance gains – Scheduled "invention" is now the majority component in all plans • Risk has increased significantly IBM Transistor Performance Improvement Gain by Traditional Scaling Gain by Innovation 100 80 60 40 500 nm 90 nm 130 nm 180 nm 250 nm 65 nm 350 nm Relative % Improvement % Relative 20 0 CMOS6X CMOS5X CMOS9S CMOS11S CMOS10S CMOS8S2 Source: IBM CMOS7S-SOI 25 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Straight Line Projections Can Be Wrong… Source: G. Moore, Intel (2003) Therefore, we need to focus on the fundamentals 26 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University To Learn More About Si Technology… EE 212 – Fabrication technology (J. Plummer) EE 316 – Si CMOS device (H.-S. P. Wong) EE 311 – Device technology (K. Saraswat) EE 309 – Semiconductor memory (H.-S. P. Wong) EE 410 – Fabrication lab (K. Saraswat) 27 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Questions? 28 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Several distinct technologies have been used to implement complex logic We are here ! $1000 buys... 1.E+12 Pentium 4 PC Vacuum tube 1.E+09 Discrete transistor Integrated circuit IBM PC 1.E+06 DEC PDP-8 1.E+03 ENIAC 1.E+00 Additions per second per Additions 1.E-03 1940 1950 1960 1970 1980 1990 2000 2010 2020 Data from R. Kurzweil, 1999, The Age of Spiritual Machines Year Source: IBM 29 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Gestation for Technologies Solid State Diode Example: Solid State Rectifier T1 26 (1874-1900) 5 T2 7 (1900-1907) Market production (Established T3 6 (1907-1913) l e Technology) Learning Period 13 years v 4 e Commercialization: L Vacuum Tube t 1907 (Entrant) n 3 T1 20 (1884-1904) e Prototype built 1900 T2 9 (1904-1913) m (Braun) ‘Research Curve’ p 2 T3 6 (1913-1919) o l Background/Infrastructure: Learning Period 15 years e T2 T3 1874 (Braun) v e 1 D Transistor T1~ 20years T1 25 (1923-1948) 0 T2 6 (1948-1954) T3 5 (1954-1959) 1870 1880 1890 1900 1910 1920 1930 Learning period 11years ~10years Integrated Circuit T1 17 (1942-1959) • To be ready for 2016 - start now narrowing T2 3 (1959-1961) T3 5(1961-1966) down options Learning Period 8 years After Ralph Cavin, SRC 30 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University International Technology Roadmap for Semiconductors The International Technology Roadmap for Semiconductors (ITRS) is an assessment of the semiconductor technology requirements. The objective of the ITRS is to ensure advancements in the performance of integrated circuits. This assessment, called roadmapping, is a cooperative effort of the global industry manufacturers and suppliers, government organizations, consortia, and universities. The ITRS identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. It is sponsored by the European Semiconductor Industry Association (ESIA), the Japan Electronics and Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), the Semiconductor Industry Association (SIA), and Taiwan Semiconductor Industry Association (TSIA). International SEMATECH is the global communication center for this activity. The ITRS team at International SEMATECH also coordinates the USA region events. 31 H.-S. Philip Wong EE 218 Department of Electrical Engineering Stanford University Emerging Research Logic Devices Source: ITRS, J. Hutchby 2003 ITRS PIDS/ERD Chapter Device Resonant 1D Spin FET RSFQ Tunneling SET Molecular QCA structures transistor Devices Not Cell Size 100 nm 0.3 µm 100 nm 100 nm 40 nm 60 nm 100 nm known Density 3E9 1E6 3E9 3E9 6E10 1E12 3E10 3E9 (cm-2) Switch 700 GH Not Not 1.2 THz 1 THz 1 GHz 30 MHz 700 GHz Speed z known known Circuit 250– 30 GHz 30 GHz 30 GHz 1 GHz <1 MHz 1 MHz 30 GHz Speed 800 GHz Switching 2×10–18 >1.4×10–17 2×10–18 >2×10–18 >1.5×10–17 1.3×10–16 >1×10–18 2×10–18 Energy, J Binary Throughput, 86 0.4 86 86 10 N/A 0.06 86 2 GBit/ns/cm http://public.itrs.net 32 H.-S.