VOICE-CONTROLLED CHESS GAME ON FPGA USING DYNAMIC TIME WARPING Varun Chirravuri, Michael Kuo Project Abstract Most modern digital chess games employ a mouse and keyboard based user interface. We change this paradigm by designing an FPGA based, voice-controlled, chess game. We will train the game to recognize specified voice commands from the players. We will use dynamic time warping to compare real-time speech samples to the trained command templates to determine what move a player wishes to make. The game will be displayed on a VGA display with all the functionality of a standard chess game. Table of Contents VOICE-CONTROLLED CHESS GAME ON FPGA USING DYNAMIC TIME WARPING ............................. i Project Abstract ............................................................................................................................................... i Table of Figures ............................................................................................................................................. iv Overview............................................................................................................................................................ 1 Audio Recognition Hardware ............................................................................................................. 1 Chess Hardware ........................................................................................................................................ 2 Keyboard Input..................................................................................................................................... 2 Chess Engine .......................................................................................................................................... 2 Graphics Engine ................................................................................................................................... 3 Description ....................................................................................................................................................... 3 Input ............................................................................................................................................................... 3 Audio Recognition Hardware ............................................................................................................. 3 DTW System Controller .................................................................................................................... 4 Dynamic Time Warping Engines.................................................................................................. 7 Valid Checker ...................................................................................................................................... 10 Finite Impulse Response Filter .................................................................................................. 11 Shift Connector .................................................................................................................................. 11 Chess Hardware ..................................................................................................................................... 12 Keyboard Input.................................................................................................................................. 12 Keyboard Entry ................................................................................................................................. 12 Keyboard Encoder ........................................................................................................................... 13 Chess Engine ....................................................................................................................................... 13 Chess Engine ....................................................................................................................................... 14 Move Checker ..................................................................................................................................... 15 Graphics Engine ................................................................................................................................ 16 Chessboard Drawer ......................................................................................................................... 16 Chess Pieces Drawer ....................................................................................................................... 17 Text Drawer ........................................................................................................................................ 18 Chess Graphics ................................................................................................................................... 18 Testing and Debugging ............................................................................................................................ 18 Audio Recognition Hardware .......................................................................................................... 18 ii DTW Engine ........................................................................................................................................ 19 DTW System Controller ................................................................................................................. 20 System Integration .......................................................................................................................... 20 Proof of Concept Testing............................................................................................................... 20 Chess Hardware ..................................................................................................................................... 21 Conclusion ..................................................................................................................................................... 22 Appendices .................................................................................................................................................... 23 Appendix A : Single DTW Test Data “Funk” v “Bridge” and “Cat” v “Dog” ................. 23 Appendix B: Letter Hit Frequency Data ...................................................................................... 25 Appendix C: Shift Connector Verilog ............................................................................................ 28 Appendix D: FIR 31 Verilog .............................................................................................................. 30 Appendix E: DTW Engine Verilog .................................................................................................. 33 Appendix F: DTW System Controller + Valid Checker Verilog ........................................ 38 Appendix G: Modified Lab 4 W/ Instantiated Modules + Debouncer Verilog .......... 46 Appendix H: Labkit File for Chess System ................................................................................. 62 Appendix I: Keyboard Entry ............................................................................................................. 74 Appendix J: Keyboard Encoder ....................................................................................................... 76 Appendix K: Chess Engine ................................................................................................................. 81 Appendix L: Move Checker ............................................................................................................... 88 Appendix L: Chessboard Drawer ................................................................................................... 97 Appendix M: Chess Pieces Drawer ................................................................................................ 98 Appendix N: Text Drawer ................................................................................................................102 Appendix O: Chess Graphics...........................................................................................................108 Appendix P: MATLAB JPG to COE ................................................................................................111 iii Table of Figures Figure 1. High Level Block Diagram Of Entire System................................................................. 1 Figure 2. Top level block diagram of chess system. ...................................................................... 2 Figure 3. Move command encoding. ..................................................................................................... 3 Figure 4. Block Diagram Of Audio Recognition Hardware. ....................................................... 4 Figure 5. Outer FSM of the DTW System Controller. .................................................................... 5 Figure 6. Inner FSM of the DTW System Controller. .................................................................... 7 Figure 7. Diagram of the DTW Engine. ................................................................................................ 8 Figure 8. Dynamic Time Warping Engine FSM............................................................................. 10 Figure 9. Block diagram of keyboard input component. ......................................................... 12 Figure 10. Block diagram of chess engine component.