Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture Initialization Considerations White Paper July 2001 Order Number: 273454-001 Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel® products are not intended for use in medical, life saving, or life sustaining applications. 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Initialization Considerations White Paper Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture Contents 1.0 Summary...........................................................................................................................5 2.0 References ........................................................................................................................6 2.1 Related Documents...............................................................................................6 Figures None Listed In This Document Tables 1 Partial Changes from Intel® i960® RM/RN I/O Processor to Intel® 80303 I/O Processor ...................................................................................5 Initialization Considerations White Paper 3 Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture This Page Intentionally Left Blank 4 Initialization Considerations White Paper Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture 1.0 Summary This paper describes some of the changes that have been made on the Intel® 80310 I/O processor chipset with Intel® XScale™ microarchitecture (80310) (ARM architecture compliant) relative to the Intel® i960® RM/RN I/O processor (i960® RM/RN or 80960RM/RN). These changes when not taken into considerations may cause the 80310 to malfunction. For a complete list of changes made to the 80310 please refer to the Migrating from Intel® 80960RM/RN I/O Processor to Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture Application Note (273419). These changes may have an impact for those trying to port an existing 80960RM/RN initialization code to the 80310. 2.0 Flash Chip Enable Signals The Intel® 80312 I/O companion chip (80312) provides two chip enable signals (RCE1# and RCE0#). On the 80960RM/RN RCE0# is used to access Flash (boot device) since the 80960RM/RN processor vectors to address 0xFEFFFF30 after reset. When using the 80310, RCE1# must be used to access Flash since the Intel® 80200 processor (80200) vectors to address 0x00000000 after reset. Table 1. Flash Bank Registers after Reset Register Name Address Reset Value FEBR0 - Flash Bank Base Address Register 0 0000154CH FE800000H FEBR1 - Flash Bank Base Address Register 1 00001550H 00000000H FBSR0 - Flash Bank Size Register 0 00001554H 8H FBSR1 - Flash Bank Size Register 1 00001554H 8H FWSR0 - Flash Wait States Register 0 0000155CH 77H FWSR0 - Flash Wait States Register 0 00001560H 77H 3.0 Intel® 80312 I/O Companion Chip Memory-Mapped Registers (MMRs) The MMRs are located between address 1000H-2000H. Since Flash must reside starting at address 00000000H, this means the Flash device overlaps onto the MMR space. Care must be taken when designing the firmware for that resides in the Flash. The firmware must not be mapped in the address range 1000-2000H. Initialization Considerations White Paper 5 Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture 4.0 Intel® 80200 Processor Core Clock The Intel® 80200 core and bus run on independent clock sources. For example, the 80200 core clock can be sourced from an oscillator whereas the bus clock is driven by the 80312. Although the core and bus run asynchronously, the ratio of the clock speeds has to be at least 3:1 for core versus bus speed. Since the 80312 drives a 100 MHz clock, the core must be made to run at a minimum of 300 MHz. When a 66 MHz oscillator is used to drive the core clock, the PLLCFG signal of the 80200 must be pulled high. This yields a core speed of 400 MHz which a 4:1 ratio. Table 2. Intel® 80200 Processor Core Clock Setup PLLCFG Signal Multiplier Core Speed (MHz) Pulled Low x3 200 Pulled High x6 400 5.0 ATU Outbound Direct Addressing Window The ATU (Address Translation Unit) Outbound Direct Addressing Window is located between address 00002000H - 80000000H. This window clearly overlaps the Flash address space. The direct addressing window is disabled after reset. Therefore, the direct addressing window should not be in the way, and access within 0x000020000 - 80000000H is claimed by the Flash device. When the application needs to use the direct addressing window and the Flash. The Flash device can be relocated by changing the base address in the FEBR1 register. This is assuming execution is transferred to SDRAM at this point. By relocating the Flash device, the user has to ensure that the 80200 exception vectors are also mapped properly. For example, the vectors are originally located starting at physical address 00000000H. Therefore by relocating the Flash, these vectors would not be present at physical address 00000000H any longer. The 80200 also provides an option of relocating the exception vectors to FFFF0000H. The user can map SDRAM in the upper part of the address space and have the vectors relocated in SDRAM at address FFFF0000H. Flash can also be relocated in the upper part of memory in such a way that address FFFF0000H would access Flash. Note that once the 80200 Memory Management Unit (MMU) is turned on, the 80200 fetches the vectors using virtual address (00000000H - 00000001CH) or (FFFF0000 - FFFF001CH). This means that the vectors can be located anywhere in physically as long as the MMU is setup to properly translate the virtual address to the physical address. 6 Initialization Considerations White Paper Intel® 80310 I/O Processor Chipset with Intel® XScale™ Microarchitecture 6.0 Programming Flash via the ATU A convenient way of programming Flash is by using the host processor to access the Flash via the ATU. This is normally done by placing the 80312 in mode 0. See the table below for various modes. Although the default inbound ATU window size is 16 MBytes, the first 4 KBytes are reserved for the Messaging Unit (MU). The first 4 Kbyte of PCI addresses are not translated, they access MU registers directly. Also the Flash Bank Base Address Register 1 (FEBR1) defaults to 00000000H after reset. Therefore, by simply programming the Primary Inbound ATU Translate Value Register (PIATVR) with 00000000H would not work because the first 4 KBytes of the Flash is not accessible because the MU is in the way. The MMRs (1000H - 2000H) also overlaps the Flash. The following example explains how the various registers can be setup to be able to access the entire Flash. Here are the assumptions: • 8 MBytes Flash device • ATU window size 16 MBytes • Program the PIATVR register